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A variable instruction stream extension to the VLIW architecture

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ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems

Pages 2 - 14

https://doi.org/10.1145/106972.106976

Published: 01 April 1991 Publication History

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References

[1]

A. Aho, et al., Compilers: Principles, Techniques and Tools.,Addison-Wesley, Reading, Mass., 1986.

Digital Library

Google Scholar

[2]

H.B. Bakoglu, et al., "IBM Second-Generation RISC Machine Organization", iCCD '89,138-142, IEEE, 1989.

Google Scholar

[3]

M. Breternitz Jr., VLIW Compilation and Architecture Synthesis, Ph.D. Thesis in preparation, Carnegie Mellon, 1991.

Google Scholar

[4]

R.P. Colwell, et al., "A VLIW Architecture for a Trace Scheduling Compiler", ASPLOS-II, ACM., 1987.

Digital Library

Google Scholar

[5]

R. P. Colwell, et al., "Architecture and Implementation of a VLIW Supercomputer", Supercomputing '90, 1990.

Digital Library

Google Scholar

[6]

K. Ebcioglu, "A Compilation Technique for Software Pipelining of Loops with Conditional Jumps", IEEE Micro.20, Dec, 1987.

Digital Library

Google Scholar

[7]

K. Ebcioglu, Some Design Ideas for a VLIW Architecture for Sequential-Natured Software, IBM Research Report, April 1988.

Google Scholar

[8]

j. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction", IEEE Transactions on Computers, July, 1981, C-30:pp. 478-490.

Google Scholar

[9]

J. A. Fisher, "Very Long Instruction Word Architectures and the ELI-512", Proc. of the lOth Syrup. Comp. Arch., IEEE Computer Society, 1983.

Digital Library

Google Scholar

[10]

M. J. Flynn, "Very High-Speed Computers", Proceedings of the iEEE, V 54, 1900-1909, Dec. 1966.

Google Scholar

[11]

Intel, "Intel 80960CA User's Manual",Intel, 1989.

Google Scholar

[12]

Intel, "Intel i860 64-bit Microprocessor Programmer's Reference Manual', Intel, 1989.

Google Scholar

[13]

J. Labrousse and G. Slavenburg, "A 50 MHz microprocessor with a VLIW architecture", ISSCC '90, IEEE, 1990.

Google Scholar

[14]

W. Maly, et al., Memory chip for 24-port global register file, Technical Report, 1990.

Google Scholar

[15]

A. Nicolau, "Percolation Scheduling: A Parallel Compilation Technique", Cornell CS. Dept Technical Report TR 85-678, May, 1985.

Digital Library

Google Scholar

[16]

G. Palmer, Design of an XiMD Computer, Masters Thesis in preparation, Carnegie Mellon, 1991.

Google Scholar

[17]

B.R.Rau, et al., "The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs", Computer, Vol 22, No. 1, January, 1989.

Digital Library

Google Scholar

[18]

H.J. Siegel, et al., "PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition", IEEE Transactions on Computers, December, 1981, C-30:pp. 934-946.

Digital Library

Google Scholar

[19]

R. StaHman, Internals of GNU CC, Free Software Foundation, Cambridge, MA, 1988.

Google Scholar

[20]

R.M. Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units, IBM Journal, Vol 11, 25-33, January 1967.

Digital Library

Google Scholar

[21]

A. Wolfe, xsim Reference Manual, Internal Report, Carnegie Mellon, 1989.

Google Scholar

[22]

A. Zaafrani, H. G. Diem, and M. T. O'Keefe, "Static Scheduling for Barrier MIMD Architectures", TR-EE 90-10, Purdue University, January 1990.

Google Scholar

Cited By

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Vedadi AWarkentin M(2018)Secure Behavior over TimeACM SIGMIS Database: the DATABASE for Advances in Information Systems10.1145/3210530.321053449:SI(39-48)Online publication date: 25-Apr-2018
https://dl.acm.org/doi/10.1145/3210530.3210534
Gupta MSanchez FLlosa J(2010)CSMTIEEE Transactions on Computers10.1109/TC.2009.9659:3(385-399)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TC.2009.96
Hampton MAsanovic KSoffa MDuesterwald E(2008)Compiling for vector-thread architecturesProceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1356058.1356085(205-215)Online publication date: 6-Apr-2008
https://dl.acm.org/doi/10.1145/1356058.1356085
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Index Terms

A variable instruction stream extension to the VLIW architecture
1. Computer systems organization
  1. Architectures
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems

April 1991

320 pages

ISBN:0897913809

DOI:10.1145/106972

Chairman:
David A. Patterson
Univ. of California, Berkeley
,
General Chair:
Bob Rau

ACM SIGARCH Computer Architecture News Volume 19, Issue 2
Apr. 1991
305 pages
ISSN:0163-5964
DOI:10.1145/106975
Editor:
David A. Patterson
Univ. of California, Berkeley
Issue’s Table of Contents
ACM SIGOPS Operating Systems Review Volume 25, Issue Special Issue
Proceedings of the 4th international conference on architectural support for programming languages and operating systems
Apr. 1991
305 pages
ISSN:0163-5980
DOI:10.1145/106974
Editor:
David A. Patterson
Univ. of California, Berkeley
Issue’s Table of Contents
ACM SIGPLAN Notices Volume 26, Issue 4
Special issue of a journal and a proceedings
Apr. 1991
305 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/106973
Editor:
David A. Patterson
Univ. of California, Berkeley
Issue’s Table of Contents

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Association for Computing Machinery

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Publication History

Published: 01 April 1991

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ASPLOS91: 4th Int'l Conference on Architecture Support for Programming Languages & Operating Systems

April 8 - 11, 1991

California, Santa Clara, USA

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Cited By

View all

Vedadi AWarkentin M(2018)Secure Behavior over TimeACM SIGMIS Database: the DATABASE for Advances in Information Systems10.1145/3210530.321053449:SI(39-48)Online publication date: 25-Apr-2018
https://dl.acm.org/doi/10.1145/3210530.3210534
Gupta MSanchez FLlosa J(2010)CSMTIEEE Transactions on Computers10.1109/TC.2009.9659:3(385-399)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TC.2009.96
Hampton MAsanovic KSoffa MDuesterwald E(2008)Compiling for vector-thread architecturesProceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1356058.1356085(205-215)Online publication date: 6-Apr-2008
https://dl.acm.org/doi/10.1145/1356058.1356085
Zhong HLieberman SMahlke S(2007)Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread ApplicationsProceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture10.1109/HPCA.2007.346182(25-36)Online publication date: 10-Feb-2007
https://dl.acm.org/doi/10.1109/HPCA.2007.346182
Hankins RChinya GCollins JWang PRakvic RWang HShen J(2006)Multiple Instruction Stream ProcessorACM SIGARCH Computer Architecture News10.1145/1150019.113649534:2(114-127)Online publication date: 1-May-2006
https://dl.acm.org/doi/10.1145/1150019.1136495
Johnson TEigenmann R(2006)Context-sensitive domain-independent algorithm composition and selectionACM SIGPLAN Notices10.1145/1133255.113400341:6(181-192)Online publication date: 11-Jun-2006
https://dl.acm.org/doi/10.1145/1133255.1134003
Zhang XGupta NGupta R(2006)Pruning dynamic slices with confidenceACM SIGPLAN Notices10.1145/1133255.113400241:6(169-180)Online publication date: 11-Jun-2006
https://dl.acm.org/doi/10.1145/1133255.1134002
Berger EZorn B(2006)DieHardACM SIGPLAN Notices10.1145/1133255.113400041:6(158-168)Online publication date: 11-Jun-2006
https://dl.acm.org/doi/10.1145/1133255.1134000
Dhurjati DKowshik SAdve V(2006)SAFECodeACM SIGPLAN Notices10.1145/1133255.113399941:6(144-157)Online publication date: 11-Jun-2006
https://dl.acm.org/doi/10.1145/1133255.1133999
Hankins RChinya GCollins JWang PRakvic RWang HShen J(2006)Multiple Instruction Stream ProcessorProceedings of the 33rd annual international symposium on Computer Architecture10.1109/ISCA.2006.29(114-127)Online publication date: 17-Jun-2006
https://dl.acm.org/doi/10.1109/ISCA.2006.29
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Recommendations

A Novel instruction stream buffer for VLIW architectures

Optimum Instruction-level Parallelism (ILP) for Superscalar and VLIW Processors

Modeling the effects of instruction queue loading on a static instruction stream micro-architecture