research-article

Online SystemC emulation acceleration

Authors:

Frank VahidAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 30 - 35

https://doi.org/10.1145/1837274.1837284

Published: 13 June 2010 Publication History

Abstract

Field-programmable gate arrays (FPGAs) have recently been used as platforms to emulate SystemC descriptions. Emulation supports in-system testing using real input and output. We previously showed emulation speed to be competitive with SystemC simulations on a PC when the emulator uses acceleration engines. A limit on the number of acceleration engines that can fit on an emulation platform creates new online problems involving runtime decisions as to when to load a SystemC process into an acceleration engine. We define the online SystemC emulation acceleration problem. In contrast to previous works that focus on statically improving SystemC (and the more general event-driven) simulations, we utilize online heuristics to manage the use of a limited number of SystemC acceleration engines in an emulation framework, where the kernel must adapt and react to dynamically changing process and event queues. We test several online heuristics and show 9x improvement over microprocessor-only emulation and 5x over statically preloaded acceleration engines. We further improve emulation performance by 10--20% by adding kernel bypass connections between acceleration engines and by adapting the online heuristics to make use of those connections.

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Cited By

Cheng ZSchmidt TLiu GDoomer R(2017)Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study2017 IEEE International High Level Design Validation and Test Workshop (HLDVT)10.1109/HLDVT.2017.8167466(74-81)Online publication date: Oct-2017
https://doi.org/10.1109/HLDVT.2017.8167466
Dömer RLiu GSchmidt T(2017)Parallel SimulationHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_19-1(1-32)Online publication date: 12-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_19-1
Dömer RLiu GSchmidt T(2017)Parallel SimulationHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_19(533-564)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_19
Show More Cited By

Index Terms

Online SystemC emulation acceleration
1. Hardware

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Published In

cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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DAC '10

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DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Cheng ZSchmidt TLiu GDoomer R(2017)Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study2017 IEEE International High Level Design Validation and Test Workshop (HLDVT)10.1109/HLDVT.2017.8167466(74-81)Online publication date: Oct-2017
https://doi.org/10.1109/HLDVT.2017.8167466
Dömer RLiu GSchmidt T(2017)Parallel SimulationHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_19-1(1-32)Online publication date: 12-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_19-1
Dömer RLiu GSchmidt T(2017)Parallel SimulationHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_19(533-564)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_19
Chen WHan XChang CLiu GDomer R(2014)Out-of-Order Parallel Discrete Event Simulation for Transaction Level ModelsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.235646933:12(1859-1872)Online publication date: Dec-2014
https://doi.org/10.1109/TCAD.2014.2356469
Weiwei Chen Xu Han Che-Wei Chang Domer R(2013)Advances in Parallel Discrete Event Simulation for Electronic System-Level DesignIEEE Design & Test10.1109/MDT.2012.222601530:1(45-54)Online publication date: Feb-2013
https://doi.org/10.1109/MDT.2012.2226015
Becker ASirowy SVahid F(2011)Just-in-time compilation for FPGA processor cores2011 Electronic System Level Synthesis Conference (ESLsyn)10.1109/ESLsyn.2011.5952282(1-6)Online publication date: Jun-2011
https://doi.org/10.1109/ESLsyn.2011.5952282

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