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LECSIM: a levelized event driven compiled logic simulation

Authors:

Peter M. MaurerAuthors Info & Claims

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

Pages 491 - 496

https://doi.org/10.1145/123186.123349

Published: 03 January 1991 Publication History

Abstract

LECSIM is a highly efficient logic simulator which integrates the advantages of event driven interpretive simulation and levelized compiled simulation. Two techniques contribute to the high efficiency. First it employs the zero-delay simulation model with levelized event scheduling to eliminate most unnecessary evaluations. Second, it compiles the central event scheduler into simple local scheduling segments which reduces the overhead of event scheduling. Experimental results show that LECSIM runs about 8-77 time faster than traditional unit-delay event-driven interpretive simulator. LECSIM also provides the option of scheduling with respect to individual gates or with respect to fan-out free blocks. When the circuit is partitioned into fan-out free blocks, the speed increases by a factor of 2-3. With partitioning, the speed of LECSIM is only about 1.5-3.4 times slower than a levelized compiled simulation for the combinational circuits we have tested.

References

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Cited By

Tian XYue CPi YLi TQu W(2024)CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618075(272-277)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10618075
Beamer SDonofrio D(2020)Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218632(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218632
Melikyan VMelikyan V(2018)Algorithmic Implementation of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration of DFSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_4(213-245)Online publication date: 13-Apr-2018
https://doi.org/10.1007/978-3-319-71637-4_4
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Index Terms

LECSIM: a levelized event driven compiled logic simulation
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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cover image ACM Conferences

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

January 1991

742 pages

ISBN:0897913639

DOI:10.1145/123186

Chairman:
Richard C. Smith

Copyright © 1991 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 January 1991

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DAC90: The 27th ACM/IEEE-CS Design Automation Conference

June 24 - 27, 1990

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DAC '90 Paper Acceptance Rate 125 of 427 submissions, 29%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Tian XYue CPi YLi TQu W(2024)CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618075(272-277)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10618075
Beamer SDonofrio D(2020)Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218632(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218632
Melikyan VMelikyan V(2018)Algorithmic Implementation of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration of DFSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_4(213-245)Online publication date: 13-Apr-2018
https://doi.org/10.1007/978-3-319-71637-4_4
Melikyan VMelikyan V(2018)Models of Logical Elements for DF ConsiderationSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_2(77-136)Online publication date: 13-Apr-2018
https://doi.org/10.1007/978-3-319-71637-4_2
Melikyan VMelikyan V(2018)General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing FactorsSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_1(1-75)Online publication date: 13-Apr-2018
https://doi.org/10.1007/978-3-319-71637-4_1
Maurer PBarros FPrähofer HHu XDenil J(2016)Time-parallel multi-delay logic simulationProceedings of the Symposium on Theory of Modeling & Simulation10.5555/2975389.2975406(1-7)Online publication date: 3-Apr-2016
https://dl.acm.org/doi/10.5555/2975389.2975406
Maurer PDe Rango FRisco Martín JCetinkaya D(2015)A second look at oblivious simulationProceedings of the Conference on Summer Computer Simulation10.5555/2874916.2874971(1-6)Online publication date: 26-Jul-2015
https://dl.acm.org/doi/10.5555/2874916.2874971
Maurer PWainer GMosterman PBarros FZacharewicz G(2013)Metamorphic differential simulation using the multi-delay timing modelProceedings of the Symposium on Theory of Modeling & Simulation - DEVS Integrative M&S Symposium10.5555/2499634.2499662(1-8)Online publication date: 7-Apr-2013
https://dl.acm.org/doi/10.5555/2499634.2499662
G RRajasekaran BM.S KS K.G SJayaram K(2013)Fundamentals of Digital system Design using VHDL and DSCH3i-manager's Journal on Computer Science10.26634/jcom.1.1.22751:1(16-21)Online publication date: 15-May-2013
https://doi.org/10.26634/jcom.1.1.2275
Saladi KSomakumar HGanapathi M(2013)Concurrency-aware compiler optimizations for hardware description languagesACM Transactions on Design Automation of Electronic Systems10.1145/2390191.239020118:1(1-16)Online publication date: 16-Jan-2013
https://dl.acm.org/doi/10.1145/2390191.2390201
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