Energy reduction with run-time partial reconfiguration (abstract only)

We study whether partial reconfiguration can be used to reduce FPGA energy consumption. In the ideal scenario, we have a hardware accelerator to accelerate certain parts of the program execution. And when the accelerator is not active, we use partial reconfiguration to unload it to reduce both static and dynamic power. However, the reconfiguration process may introduce a high energy overhead, thus it is unclear whether this approach is feasible. To approach this problem, we identify the conditions under which partial reconfiguration can be used to reduce energy consumption, and we propose solutions to minimize the configuration energy overhead. The results of our study show that by using partial reconfiguration to eliminate the power consumption of the accelerator when it is inactive, we can accelerate program execution and at the same time reduce the overall energy consumption by half.