Abstract
Power consumption reduction is crucial for portable equipments and for those in remote locations, whose battery replacement is impracticable. P\(^2\)IP is an architecture targeting real-time embedded image and video processing, which combines runtime reconfigurable processing, low-latency and high performance. Being a configurable architecture allows the combination of powerful video processing operators (Processing Elements or PEs) to build the target application. However, many applications do not require all PEs available. Remaining idle, these PEs still represent a power consumption problem that Partial Reconfiguration can mitigate. To assess the impact on energy consumption, another P\(^2\)IP implementation based on Partial Reconfiguration was developed and tested with three different image processing applications. Measurements have been made to analyze energy consumption when executing each of three applications. Results show that compared to the original implementation of the architecture use of Partial Reconfiguration leads to power savings of up to 45%.
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The authors would like to thank the support from the Coordination of Superior Level Staff Improvement (CAPES), brazilian sponsoring agency, and also the Electronics and Microelectronics Department from the University of Mons, Belgium, for the support offered to the development of this work.
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Avelino, Á., Obac, V., Harb, N., Valderrama, C., Albuquerque, G., Possa, P. (2017). LP-P\(^2\)IP: A Low-Power Version of P\(^2\)IP Architecture Using Partial Reconfiguration. In: Wong, S., Beck, A., Bertels, K., Carro, L. (eds) Applied Reconfigurable Computing. ARC 2017. Lecture Notes in Computer Science(), vol 10216. Springer, Cham. https://doi.org/10.1007/978-3-319-56258-2_2
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