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TIM: a timing package for two-phase, level-clocked circuitry

Authors:

Marios C. Papaefthymiou,

Keith H. RandallAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 497 - 502

https://doi.org/10.1145/157485.164998

Published: 01 July 1993 Publication History

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M. C. Papaefthymiou and K. H. Randall. TIM: an interactive timing optimization tool for level-clocked circuits. July 1992. User's Guide and Reference Manual, under preparation.

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Cited By

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Cheng HWang HZhang MHand DBeerel P(2019)Automatic Retiming of Two-Phase Latch-Based Resilient CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284663138:7(1305-1316)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2846631
Wang HZhang MBeerel P(2017)Retiming of Two-Phase Latch-Based Resilient CircuitsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062312(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062312
Wang SLiang YZhang W(2017)FlexCLProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062251(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062251
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Index Terms

TIM: a timing package for two-phase, level-clocked circuitry
1. Hardware
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Graph algorithms

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Information & Contributors

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Cheng HWang HZhang MHand DBeerel P(2019)Automatic Retiming of Two-Phase Latch-Based Resilient CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284663138:7(1305-1316)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2846631
Wang HZhang MBeerel P(2017)Retiming of Two-Phase Latch-Based Resilient CircuitsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062312(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062312
Wang SLiang YZhang W(2017)FlexCLProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062251(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062251
Menon RThornton M(2012)Global Multiple-Valued Clock Approach for High- Performance Multi-phase Clock Integrated CircuitsProceedings of the 2012 IEEE 42nd International Symposium on Multiple-Valued Logic10.1109/ISMVL.2012.30(19-24)Online publication date: 14-May-2012
https://dl.acm.org/doi/10.1109/ISMVL.2012.30
Zhou H(2008)A new efficient retiming algorithm derived by formal manipulationACM Transactions on Design Automation of Electronic Systems10.1145/1297666.129767313:1(1-19)Online publication date: 6-Feb-2008
https://dl.acm.org/doi/10.1145/1297666.1297673
Kumar N. Lalgudi (2006)DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling32nd Design Automation Conference10.1109/DAC.1995.249964(304-309)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.249964
Liu XPapaefthymiou MFriedman E(2006)Retiming and clock scheduling for digital circuit optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.98025821:2(184-203)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.980258
Maheshwari NSapatnekar S(2006)Optimizing large multiphase level-clocked circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.78411818:9(1249-1264)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.784118
Lalgudi KPapaefthymiou M(2006)Retiming edge-triggered circuits under general delay modelsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66422216:12(1393-1408)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.664222
Sakallah KWalker DNassif S(2003)Timing, Test and Manufacturing OverviewThe Best of ICCAD10.1007/978-1-4615-0292-0_43(551-562)Online publication date: 2003
https://doi.org/10.1007/978-1-4615-0292-0_43
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