Article

Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits

Authors:

Michael R. Dagenais,

Nicholas C. RuminAuthors Info & Claims

Proceedings of the fifth MIT conference on Advanced research in VLSI

Pages 19 - 33

Published: 02 January 1988 Publication History

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Ishii ALeiserson CPapaefthymiou M(1997)Optimizing two-phase, level-clocked circuitryJournal of the ACM10.1145/256292.25630144:1(148-199)Online publication date: 15-Jan-1997
https://dl.acm.org/doi/10.1145/256292.256301
Papaefthymiou MRandall KDunlop A(1993)TIMProceedings of the 30th international Design Automation Conference10.1145/157485.164998(497-502)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164998
Kawarabayashi MShenoy NSangiovanni-Vincentelli ADunlop A(1993)A verification technique for gated clockProceedings of the 30th international Design Automation Conference10.1145/157485.164624(123-127)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164624
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Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits

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The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are ...
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Proceedings of the fifth MIT conference on Advanced research in VLSI

January 1988

366 pages

ISBN:026201100X

Chairman:
Jonathan Allen
The Massachusetts Institute of Technology, Cambridge

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MIT Press

Cambridge, MA, United States

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Published: 02 January 1988

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Ishii ALeiserson CPapaefthymiou M(1997)Optimizing two-phase, level-clocked circuitryJournal of the ACM10.1145/256292.25630144:1(148-199)Online publication date: 15-Jan-1997
https://dl.acm.org/doi/10.1145/256292.256301
Papaefthymiou MRandall KDunlop A(1993)TIMProceedings of the 30th international Design Automation Conference10.1145/157485.164998(497-502)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164998
Kawarabayashi MShenoy NSangiovanni-Vincentelli ADunlop A(1993)A verification technique for gated clockProceedings of the 30th international Design Automation Conference10.1145/157485.164624(123-127)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164624
Shenoy NBrayton RSangiovanni-Vincentelli ATrevillyan LLightner M(1992)Graph algorithms for clock schedule optimizationProceedings of the 1992 IEEE/ACM international conference on Computer-aided design10.5555/304032.304073(132-136)Online publication date: 8-Nov-1992
https://dl.acm.org/doi/10.5555/304032.304073
Shenoy NSingh KBrayton RSangiovanni-Vincentelli ASchweikert D(1992)On the temporal equivalence of sequential circuitsProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.149549(405-409)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.149549
Zahir RFichtner WAmbler TJess JDe Man H(1991)Specification of timing constraints for controller synthesisProceedings of the conference on European design automation10.5555/951513.951581(316-322)Online publication date: 25-Feb-1991
https://dl.acm.org/doi/10.5555/951513.951581

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Recommendations

Testability analysis of MOS VLSI circuits

MOS current mode circuits: analysis design and variability

Design and Clocking of VLSI Multipliers

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