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High-level transformations for minimizing syntactic variances

Authors:

Viraphol Chaiyakul,

Daniel D. Gajski,

Loganath RamachandranAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 413 - 418

https://doi.org/10.1145/157485.164956

Published: 01 July 1993 Publication History

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Badier HPilato CLann JCoussy PGogniat G(2021)Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474200(52-55)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474200
Badier HLe Lann JCoussy PGogniat G(2021)Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the CloudBehavioral Synthesis for Hardware Security10.1007/978-3-030-78841-4_5(71-93)Online publication date: 28-May-2021
https://doi.org/10.1007/978-3-030-78841-4_5
Zhang TSaab DAbraham J(2017)Automatic Assertion Generation for Simulation, Formal Verification and Emulation2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.88(471-476)Online publication date: Jul-2017
https://doi.org/10.1109/ISVLSI.2017.88
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Index Terms

High-level transformations for minimizing syntactic variances
1. Hardware
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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DAC93

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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June 22 - 26, 2025

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Cited By

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Badier HPilato CLann JCoussy PGogniat G(2021)Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474200(52-55)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474200
Badier HLe Lann JCoussy PGogniat G(2021)Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the CloudBehavioral Synthesis for Hardware Security10.1007/978-3-030-78841-4_5(71-93)Online publication date: 28-May-2021
https://doi.org/10.1007/978-3-030-78841-4_5
Zhang TSaab DAbraham J(2017)Automatic Assertion Generation for Simulation, Formal Verification and Emulation2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.88(471-476)Online publication date: Jul-2017
https://doi.org/10.1109/ISVLSI.2017.88
Chauhan VGala NKamakoti V(2016)ChADDProceedings of the 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2016.44(499-504)Online publication date: 4-Jan-2016
https://dl.acm.org/doi/10.1109/VLSID.2016.44
Shaheen AHussin FHamid NAli N(2014)Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram2014 5th International Conference on Intelligent and Advanced Systems (ICIAS)10.1109/ICIAS.2014.6869530(1-5)Online publication date: Jun-2014
https://doi.org/10.1109/ICIAS.2014.6869530
Shaheen AHussin FHamid NAli N(2013)Automatic generation of test instructions for structural faults in processor cores using satisfiability2013 International SoC Design Conference (ISOCC)10.1109/ISOCC.2013.6864058(388-391)Online publication date: Nov-2013
https://doi.org/10.1109/ISOCC.2013.6864058
Raik JRepinski UChepurov AHantson HUbar RJenihhin M(2013)Automated design error debug using high-level decision diagrams and mutation operatorsMicroprocessors and Microsystems10.1016/j.micpro.2012.11.00437:4-5(505-513)Online publication date: Jun-2013
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Viilukas TKarputkin ARaik JJenihhin MUbar RFujiwara H(2012)Identifying Untestable Faults in Sequential Circuits Using Test Path ConstraintsJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5312-528:4(511-521)Online publication date: 1-Aug-2012
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Raik JRepinski UJenihhin MChepurov A(2011)High-Level Decision Diagram Simulation for Diagnosis and Soft-Error AnalysisDesign and Test Technology for Dependable Systems-on-Chip10.4018/978-1-60960-212-3.ch013(294-309)Online publication date: 2011
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OBIEN MOHTAKE SFUJIWARA H(2011)F-Scan: A DFT Method for Functional Scan at RTLIEICE Transactions on Information and Systems10.1587/transinf.E94.D.104E94-D:1(104-113)Online publication date: 2011
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