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Starfire: Extending the SMP Envelope

Published: 01 January 1998 Publication History

Abstract

The Sun Microsystems Starfire Ultra 10000 server is today's largest uniform-memory-access symmetric multiprocessor system. It uses an active centerplane with four address routers, and a 16x16 data crossbar to provide 64 processors with a memory bandwidth of 10,667 MBps. The use of point-to-point routers allows the system to be dynamically reconfigured into multiple hardware-protected operating system domains, with hot-swappable boards. This paper describes the interconnect implementation, and compares its price and performance to other multiprocessor architectures using the TPC-D benchmark.

References

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B. Catanzaro, Multiprocessor System Architectures, Prentice Hall, Englewood Cliffs, N.J., 1994.
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K. Normoyle, et al., "The UltraSPARC Port Architecture," Proc. Hot Interconnects Symp. III, 1995, available from author at [email protected].
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A. Singhal, et al., "Gigaplane: A High Performance Bus for Large SMPs," Proc. Hot Interconnects Symp. IV, 1996, available from author at [email protected].
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A. Charlesworth, et al., "Gigaplane-XB: Extending the Ultra Enterprise Family," Proc. Hot Interconnects Symp. V, 1997, http://HTTP.CS.Berkeley.EDU/culler/hoti97/E10000.ps.
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Transaction Processing Performance Council, TPC Benchmark Results; see http://www.tpc.org/bench.results.html for current results.
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J.J. Dongarra, "Performance of Various Computers Using Standard Linear Equations Software" (see http://performance.netlib.org/performance/html/PERFORM.ps for current report).
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The Standard Performance Evaluation Corp., SPEC CPU95 Results (see http://www.specbench.org/osg/cpu95/results/ for current results).

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Information & Contributors

Information

Published In

cover image IEEE Micro
IEEE Micro  Volume 18, Issue 1
January 1998
140 pages

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 January 1998

Author Tags

  1. Interconnect
  2. TPC-D
  3. domains
  4. shared memory
  5. uniform memory access

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