research-article

Introducing the Intel i860 64-Bit Microprocessor

Authors:

Les Kohn,

Neal MargulisAuthors Info & Claims

IEEE Micro, Volume 9, Issue 4

Pages 15 - 30

https://doi.org/10.1109/40.31485

Published: 01 July 1989 Publication History

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Abstract

The authors describe the single-chip i860 CPU, a 64-bit, RISC (reduced-instruction-set-computer)-based microprocessor that executes parallel instructions using mainframe and supercomputer architectural concepts. They designed the 1,000,000-transistor, 10-mm*15-mm processor for balanced integer, floating-point, and graphics performance. They discuss the RISC core, memory management, floating-point unit, graphics, bus interface, software support, and interfacing to a DRAM system

Reference

[1]

1. ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic, IEEE Computer Society Press, Los Alamitos, Calif., 1985.

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Kaxiras SRos AMendelson A(2013)A new perspective for efficient virtual-cache coherenceProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485968(535-546)Online publication date: 23-Jun-2013
Hennessy JPatterson D(2011)Computer Architecture, Fifth EditionundefinedOnline publication date: 29-Sep-2011
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Introducing the Intel i860 64-Bit Microprocessor

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Published In

IEEE Micro Volume 9, Issue 4

July 1989

84 pages

ISSN:0272-1732

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Publisher

IEEE Computer Society Press

Washington, DC, United States

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Published: 01 July 1989

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Kaxiras SRos A(2013)A new perspective for efficient virtual-cache coherenceACM SIGARCH Computer Architecture News10.1145/2508148.248596841:3(535-546)Online publication date: 23-Jun-2013
Kaxiras SRos AMendelson A(2013)A new perspective for efficient virtual-cache coherenceProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485968(535-546)Online publication date: 23-Jun-2013
Hennessy JPatterson D(2011)Computer Architecture, Fifth EditionundefinedOnline publication date: 29-Sep-2011
Cekleov MDubois M(1997)Virtual-Address Caches, Part 2IEEE Micro10.1109/40.64159917:6(69-74)Online publication date: 1-Nov-1997
Cekleov MDubois M(1997)Virtual-Address Caches Part 1IEEE Micro10.1109/40.62121517:5(64-71)Online publication date: 1-Sep-1997
Lee RSmith M(1996)Guest Editors' IntroductionIEEE Micro10.1109/MM.1996.52692016:4(6-9)Online publication date: 1-Aug-1996
Gao GWong YNing Q(1991)A timed Petri-net model for fine-grain loop schedulingProceedings of the 1991 conference of the Centre for Advanced Studies on Collaborative research10.5555/962111.962140(395-415)Online publication date: 28-Oct-1991
Gao GWong YNing Q(1991)A timed Petri-net model for fine-grain loop schedulingACM SIGPLAN Notices10.1145/113446.11346326:6(204-218)Online publication date: 1-May-1991
Gao GWong YNing QWise D(1991)A timed Petri-net model for fine-grain loop schedulingProceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation10.1145/113445.113463(204-218)Online publication date: 1-May-1991
Kohn LMargulis NBailey F(1989)The i860 64-bit supercomputing microprocessorProceedings of the 1989 ACM/IEEE conference on Supercomputing10.1145/76263.76313(450-456)Online publication date: 1-Aug-1989
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The i860^TM 64-bit supercomputing microprocessor