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Performance Analysis of k-ary n-cube Interconnection Networks

Published: 01 June 1990 Publication History

Abstract

VLSI communication networks are wire-limited, i.e. the cost of a network is not a function of the number of switches required, but rather a function of the wiring density required to construct the network. Communication networks of varying dimensions are analyzed under the assumption of constant wire bisection. Expressions for the latency, average case throughput, and hot-spot throughput of k-ary n-cube networks with constant bisection that agree closely with experimental measurements are derived. It is shown that low-dimensional networks (e.g. tori) have lower latency and higher hot-spot throughput than high-dimensional networks (e.g. binary n-cubes) with the same bisection width.

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Roger Raymond Schell

Dally presents a valuable set of basic design considerations for the VLSI implementations of concurrent computers. He analyzes the theoretical impact of the physical constraints of VLSI systems, especially limited wire density, for interconnection networks. Based on reasonable assumptions and approximations, he derives detailed mathematical expressions for estimating the performance of a range of network alternatives. Both the average network latency and the throughput are estimated, and several interesting results are presented graphically. The primary conclusion is that, with VLSI constraints, networks with fewer wide channels provide lower latency and higher throughput than those with a larger number of narrow channels. The paper seems intended for readers with research background and interests who are reasonably conversant with the issues and terminology of VLSI communications networks. The needed definitions are often terse and in some cases only implicit, although Dally provides a relevant bibliography. The reader is left with the sense that the author is disproportionately emphasizing those factors that support his primary conclusions. His reasoning is carefully presented, however, and the mathematics, which is key to the paper, is accurate and precise without excessive detail or length. Overall, the paper is readable and informative.

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Information

Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 39, Issue 6
June 1990
133 pages
ISSN:0018-9340
Issue’s Table of Contents

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IEEE Computer Society

United States

Publication History

Published: 01 June 1990

Author Tags

  1. VLSI communication networks
  2. VLSI.
  3. average case throughput
  4. k-ary n-cube interconnection networks
  5. low-dimensional networks
  6. multiprocessor interconnection networks
  7. switches

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