A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories
Authors: 
Albert Lee, Hochul Lee, Farbod Ebrahimi, Bonnie Lam, Wei-Hao Chen, Meng-Fan Chang, Pedram Khalili Amiri, Kang-L. WangAuthors Info & Claims
Pages 272 - 279
Abstract
Resistance-based memory devices are considered as a strong candidate for next-generation nonvolatile memories as well as potential application in high density embedded cache. These devices can be programmed to different resistance states by applying electrical bias. Read operation then senses the programmed state by discharging a shared data line through the memory cell. However, as the dimensions of the device scale down, its resistance increases and the distribution widens, which leads to reduced sensing margins and degradation in read performance. In the proposed dual-data line (DDL) read scheme, we recycle current flowing through the memory cell during the read operation to create an additional voltage swing on a secondary data line, and combine it with the signal on the original data line to reduce sensing time and energy. Performance comparison with the conventional read scheme is derived theoretically by using circuit analysis and verified through simulation on an array critical path constructed in 65-nm technology. Results show that the DDL scheme can improve sensing margins by an average of 86%, which translates to a sensing time reduction of 47%, across various device conditions. For the same read performance, the sensing energy is decreased by 48%.
References
[1]
Y. Lu, “ Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications,” in IEDM Tech. Dig., 2016, pp. 26.1.1–26.1.4.
[2]
J. J. Kan, “ Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance,” in IEDM Tech. Dig., 2017, pp. 27.4.1–27.4.4.
[3]
W. Kang, “ Yield and reliability improvement techniques for emerging nonvolatile STT-MRAM,” IEEE J. Emerg. Sel. Topics Circuits Syst., vol. Volume 5, no. Issue 1, pp. 28–39, 2015.
[4]
W. Kang, L. Zhang, J.-O. Klein, Y. Zhang, D. Ravelosona, and W. Zhao, “ Reconfigurable codesign of STT-MRAM under process variations in deeply scaled technology,” IEEE Trans. Electron Devices, vol. Volume 62, no. Issue 6, pp. 1769–1777, 2015.
[5]
S.-W. Chung, “ 4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure,” in IEDM Tech. Dig., 2016, pp. 21–27.
[6]
S. Ikeda, “ A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction,” Nature Mater., vol. Volume 9, no. Issue 9, pp. 721–724, 2010.
[7]
Y. Huai, F. Albert, P. Nguyen, M. Pakala, and T. Valet, “ Observation of spin-transfer switching in deep submicron-sized and low-resistance magnetic tunnel junctions,” Appl. Phys. Lett., vol. Volume 84, no. Issue 16, pp. 3118–3120, 2004.
[8]
I. M. Miron, “ Perpendicular switching of a single ferromagnetic layer induced by in-plane current injection,” Nature, vol. Volume 476, no. Issue 7359, pp. 189–193, 2011.
[9]
L. Liu, C.-F. Pai, Y. Li, H. W. Tseng, D. C. Ralph, and R. A. Buhrman, “ Spin-torque switching with the giant spin Hall effect of tantalum,” Science, vol. Volume 336, no. Issue 6081, pp. 555–558, 2012.
[10]
T. Jungwirth, J. Wunderlich, and K. Olejnik, “ Spin Hall effect devices,” Nature Mater., vol. Volume 11, pp. 382–390, 2012.
[11]
K. L. Wang, J. G. Alzate, and P. K. Amiri, “ Low-power non-volatile spintronic memory: STT-RAM and beyond,” J. Phys. D, Appl. Phys., vol. Volume 46, no. Issue 7, p. pp.74003, 2013.
[12]
J. G. Alzate, “ Voltage-induced switching of nanoscale magnetic tunnel junctions,” in IEDM Tech. Dig., 2012, pp. 29.5.1–29.5.4.
[13]
W.-G. Wang, M. Li, S. Hageman, and C. L. Chien, “ Electric-field-assisted switching in magnetic tunnel junctions,” Nature Mater., vol. Volume 11, pp. 64–68, 2012.
[14]
Y. Shiota, T. Nozaki, F. Bonell, S. Murakami, T. Shinjo, and Y. Suzuki, “ Induction of coherent magnetization switching in a few atomic layers of FeCo using voltage pulses,” Nature Mater., vol. Volume 11, no. Issue 1, pp. 39–43, 2012.
[15]
S. Kanai, M. Yamanouchi, S. Ikeda, Y. Nakatani, F. Matsukura, and H. Ohno, “ Electric field-induced magnetization reversal in a perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction,” Appl. Phys. Lett., vol. Volume 101, no. Issue 12, p. pp.122403, 2012.
[16]
W. Zhao, “ Synchronous non-volatile logic gate design based on resistive switching memories,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. Volume 61, no. Issue 2, pp. 443–454, 2014.
[17]
A. Bricalli, E. Ambrosi, M. Laudato, M. Maestro, R. Rodriguez, and D. Ielmini, “ SiOx-based resistive switching memory (RRAM) for crossbar storage/select elements with high on/off ratio,” in IEDM Tech. Dig., 2016, pp. 3–4.
[18]
C. Nail, “ Understanding RRAM endurance, retention and window margin trade-off using experimental results and simulations,” in IEDM Tech. Dig., 2017, pp. 4.5.1–4.5.4.
[19]
M.-F. Chang, “ 19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2014, pp. 332–333.
[20]
J. Zahurak, “ Process integration of a 27 nm, 16 Gb Cu ReRAM,” in IEDM Tech. Dig., 2014, pp. 2–6.
[21]
A. Kawahara, “ An 8 Mb multi-layered cross-point ReRAM macro with 443 MB/s write throughput,” IEEE J. Solid-State Circuits, vol. Volume 48, no. Issue 1, pp. 178–185, 2013.
[22]
R. Fackenthal, “ A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2014, pp. 338–339.
[23]
T.-Y. Liu, “ A 130.7-<inline-formula><tex-math notation=LaTeX>$mm^{2}$</tex-math></inline-formula> 2-layer 32-Gb ReRAM memory device in 24-nm technology,” IEEE J. Solid-State Circuits, vol. Volume 49, no. Issue 1, pp. 140–153, 2014.
[24]
W. Kim, “ ALD-based confined PCM with a metallic liner toward unlimited endurance,” in IEDM Tech. Dig., 2016, pp. 2–4.
[25]
W. C. Chien, “ Reliability study of a 128Mb phase change memory chip implemented with doped Ga-Sb-Ge with extraordinary thermal stability,” in IEDM Tech. Dig., 2016, pp. 21.1.1–21.1.4.
[26]
H. Y. Cheng, “ Novel fast-switching and high-data retention phase-change memory based on new Ga-Sb-Ge material,” in IEDM Tech. Dig., 2016, pp. 3.5.1–3.5.4.
[27]
H. Y. Cheng, “ A high performance phase change memory with fast switching speed and high temperature retention by engineering the GexSbyTez phase change material,” IEDM Tech. Dig., 2011, pp. 3.4.1–3.4.4.
[28]
G. F. Close, “ A 512 Mb phase-change memory (PCM) in 90 nm CMOS achieving 2b/cell,” in Proc. Int. Symp. VLSI Circuits, Jun. 2011, pp. 202–203.
[29]
Y. Choi, “ A 20 nm 1.8 V 8 Gb PRAM with 40 MB/s program bandwidth,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. Volume 55 . Feb. 2012, pp. 46–47.
[30]
H. Y. Cheng, “ A thermally robust phase change memory by engineering the Ge/N concentration in (Ge, N)xSbyTez phase change material,” in IEDM Tech. Dig., 2012, pp. 31.1.1–31.1.4.
[31]
C. W. Park, C. Park, W. Y. Choi, D. Seo, C. Jeong, and I. H. Cho, “ Scaling down characteristics of vertical channel phase change random access memory (VPCRAM),” JSTS J. Semicond. Technol. Sci., vol. Volume 14, no. Issue 1, pp. 48–52, 2014.
[32]
Y. Hayakawa, “ Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application,” in Proc. Int. Symp. VLSI Technol., Jun. 2015, pp. T14–T15.
[33]
B. J. Choi, “ Electrical performance and scalability of Pt dispersed SiO2 nanometallic resistance switch,” Nano Lett., vol. Volume 13, no. Issue 7, pp. 3213–3217, 2013.
[34]
F. Xiong, “ Towards ultimate scaling limits of phase-change memory,” in IEDM Tech. Dig., 2016, pp. 1–4.
[35]
K. Tsunoda, “ Area dependence of thermal stability factor in perpendicular STT-MRAM analyzed by bi-directional data flipping model,” in IEDM Tech. Dig., 2014, pp. 13–19.
[36]
K.-S. Li, “ Utilizing sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication,” in Proc. Int. Symp. VLSI Technol., Jun. 2014, pp. 1–2.
[37]
J. J. Nowak, “ Dependence of voltage and size on write error rates in spin-transfer torque magnetic random-access memory,” IEEE Magn. Lett., vol. Volume 7, 2016, Art. no. .
[38]
A. Lee, C.-C. Lin, T.-C. Yang, and M.-F. Chang, “ An embedded ReRAM using a small-offset sense amplifier for low-voltage operations,” in Proc. Int. Symp. VLSI Design, Autom. Test, Apr. 2015, pp. 1–4.
[39]
C.-C. Lin, “ A 256b-wordlength ReRAM-based TCAM with 1ns search-time and <inline-formula><tex-math notation=LaTeX>$14{\times}$</tex-math></inline-formula> improvement in wordlength-energyefficiency-density product using 2.5T1R cell,” in Int. Solid-State Circuits Conf. Tech. Dig. Papers, Jan./Feb. 2016, pp. 136–137.
[40]
M. Khayatzadeh, F. Frustaci, D. Blaauw, D. Sylvester, and M. Alioto, “ A reconfigurable sense amplifier with 3X offset reduction in 28 nm FDSOI CMOS,” in Proc. Int. Symp. VLSI Circuits, Jun. 2015, pp. C270–C271.
- A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories
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Published: 01 February 2018
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