An 8 Mb multi-layered cross-point ReRAM macro with 443 MB/s write throughput

A Kawahara, R Azuma, Y Ikeda, K Kawai… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
A Kawahara, R Azuma, Y Ikeda, K Kawai, Y Katoh, Y Hayakawa, K Tsuji, S Yoneda…
IEEE Journal of Solid-State Circuits, 2012ieeexplore.ieee.org
An 8-Mb multi-layered cross-point resistive RAM (ReRAM) macro has been developed with
443 MB/s write throughput (64-bits parallel write per 17.2-ns cycle), which is almost twice as
fast as competing methods. It uses the fast switching performance of TaOx ReRAM and a
new write architecture to reduce the sneak current in a cross-point cell array structure based
on an 0.18-μm process. First, a bidirectional diode as a memory cell select element is
developed to reduce the sneak current. Second, PMOS and NMOS are used select …
An 8-Mb multi-layered cross-point resistive RAM (ReRAM) macro has been developed with 443 MB/s write throughput (64-bits parallel write per 17.2-ns cycle), which is almost twice as fast as competing methods. It uses the fast switching performance of TaOx ReRAM and a new write architecture to reduce the sneak current in a cross-point cell array structure based on an 0.18-μm process. First, a bidirectional diode as a memory cell select element is developed to reduce the sneak current. Second, PMOS and NMOS are used select transistors in the source follower to realize stable switching for the selected cell in the multi-layered cross-point structure. Third, a hierarchical bitline (BL) structure is employed with a short bitline. Fourth, multi-bit write architecture is developed to realize fast write operation and to suppress the sneak current.
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