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Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking

Published: 01 July 2010 Publication History

Abstract

Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be even pushed further by properly matching the partition to the memory access patterns. When leakage energy comes into play, however, idle memory blocks must be put into a proper low-leakage sleep state to actually save energy when not accessed. In this case, the matching becomes an instance of the power management problem, because moving to and from this sleep state requires additional energy. In this work, we propose an effective solution to the problem of the leakage-aware partitioning of a memory into disjoint subblocks; in particular, we target scratchpad memories, which are commonly used in some embedded systems as a replacement for caches. We show that, although the solution space is extremely large (for a N--block partition, all the combinations of N-1 address boundaries) and nonconvex, it is possible to prove a nontrivial property that considerably reduces the number of partition boundaries to be enumerated, therefore, making exhaustive exploration feasible. We are thus able to provide an optimal solution to the leakage-aware partitioning problem. Experiments on a different sets of embedded applications have shown that total energy savings larger than 60 percent on average can be obtained, with a marginal overhead in execution time, thanks to an effective implementation of the low-leakage sleep state.

Cited By

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  • (2021)Fast and Predictable Non-Volatile Data Memory for Real-Time Embedded SystemsIEEE Transactions on Computers10.1109/TC.2020.298826170:3(359-371)Online publication date: 9-Feb-2021
  • (2019)Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip DesignACM Transactions on Embedded Computing Systems10.1145/335658318:5(1-25)Online publication date: 9-Oct-2019
  • (2015)Optimum design of a banked memory with power management for wireless sensor networksWireless Networks10.1007/s11276-014-0763-521:1(81-94)Online publication date: 1-Jan-2015
  • Show More Cited By

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Information

Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 59, Issue 7
July 2010
144 pages

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 July 2010

Author Tags

  1. Power optimization
  2. Power optimization, leakage power, embedded design, memory hierarchy, scratchpad memory, partitioning algorithm.
  3. embedded design
  4. leakage power
  5. memory hierarchy
  6. partitioning algorithm.
  7. scratchpad memory

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Cited By

View all
  • (2021)Fast and Predictable Non-Volatile Data Memory for Real-Time Embedded SystemsIEEE Transactions on Computers10.1109/TC.2020.298826170:3(359-371)Online publication date: 9-Feb-2021
  • (2019)Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip DesignACM Transactions on Embedded Computing Systems10.1145/335658318:5(1-25)Online publication date: 9-Oct-2019
  • (2015)Optimum design of a banked memory with power management for wireless sensor networksWireless Networks10.1007/s11276-014-0763-521:1(81-94)Online publication date: 1-Jan-2015
  • (2014)Reducing cache leakage energy for hybrid SPM-cache architecturesProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656124(1-9)Online publication date: 12-Oct-2014
  • (2012)NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded SystemsJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5295-228:3(349-363)Online publication date: 1-Jun-2012

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