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A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors

Published: 26 May 2011 Publication History

Abstract

Thread Level Speculation (TLS) is a technique aims at boosting the performance of sequential programs running on Chip Multiprocessors (CMPs) by automatically parallelizing them. It exempts programmers from the heavy task of parallel programming. But its performance may suffer from frequent squashing caused by inter-thread data dependency violation. In this paper, we propose a Network-on-Chip (NoC) in CMP that employs a priority-aware packet arbitration policy. Packet scheduling guided by such policy reduces the occurrence of TLS squashes. Simulation results with 5 applications show that our policy reduces squashes by 22% in best case and 15% on average. Moreover, our priority aware approach could be generalized to similar scenarios in which different threads running on CMP manifest different priorities.

Cited By

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  • (2018)Critical packet prioritisation by slack-aware re-routing in on-chip networksProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306631(1-8)Online publication date: 4-Oct-2018
  • (2016)A Survey on Thread-Level Speculation TechniquesACM Computing Surveys10.1145/293836949:2(1-39)Online publication date: 30-Jun-2016
  • (2016)New Data Structures to Handle Speculative Parallelization at RuntimeInternational Journal of Parallel Programming10.1007/s10766-014-0347-044:3(407-426)Online publication date: 1-Jun-2016
  • Show More Cited By

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Information

Published In

cover image Guide Proceedings
ISPA '11: Proceedings of the 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications
May 2011
337 pages
ISBN:9780769544281

Publisher

IEEE Computer Society

United States

Publication History

Published: 26 May 2011

Author Tags

  1. network on chip
  2. prioirity
  3. squash
  4. thread level speculation

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Cited By

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  • (2018)Critical packet prioritisation by slack-aware re-routing in on-chip networksProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306631(1-8)Online publication date: 4-Oct-2018
  • (2016)A Survey on Thread-Level Speculation TechniquesACM Computing Surveys10.1145/293836949:2(1-39)Online publication date: 30-Jun-2016
  • (2016)New Data Structures to Handle Speculative Parallelization at RuntimeInternational Journal of Parallel Programming10.1007/s10766-014-0347-044:3(407-426)Online publication date: 1-Jun-2016
  • (2015)Data Criticality in Network-On-Chip DesignProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2786593(1-8)Online publication date: 28-Sep-2015
  • (2015)Position-aware thread-level speculative parallelization for large-scale chip-multiprocessorProceedings of the 12th ACM International Conference on Computing Frontiers10.1145/2742854.2742866(1-8)Online publication date: 6-May-2015

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