Test Generation for State Retention Logic

Designs using advanced low power techniques like Multi- Supply Multi-Voltage and Power Shutoff bring with them a new set of challenges that manufacturing test must deal with carefully. These designs have low power components – isolation cells, retention ...

Power management in system-on-chip (SoC) has become one of the most crucial techniques for mobile devices. Among many intellectual properties (IPs) of SoC, a microprocessor, which is one of the major power consumers in the system, is a key component in ...

Retention registers/latches are commonly applied to power-gated circuits for state retention during the sleep mode. Recent studies have shown that applying uniform multi-bit retention registers (MBRRs) can reduce the storage size, and hence save more ...