It is generally known that a considerable portion of flip-flops in circuits is occupied by the ones with mux-feedback loop (called self-loop), which are the critical (inherently unavoidable) bottleneck in minimizing total (always-on) storage size for ...

Retention registers/latches are commonly applied to power-gated circuits for state retention during the sleep mode. Recent studies have shown that applying uniform multi-bit retention registers (MBRRs) can reduce the storage size, and hence save more ...

Power management in system-on-chip (SoC) has become one of the most crucial techniques for mobile devices. Among many intellectual properties (IPs) of SoC, a microprocessor, which is one of the major power consumers in the system, is a key component in ...

Designs using advanced low power techniques like Multi- Supply Multi-Voltage and Power Shutoff bring with them a new set of challenges that manufacturing test must deal with carefully. These designs have low power components – isolation cells, retention ...

This work presents a low-power dual-edge triggered static scanable flip-flop that uses reduced swing-clock and -data to manage dynamic power. The circuit employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power,...

As low power designs with multiple switchable power domains become more common, there is a need to ensure that the low power component structures in the design –such as isolation cells, state retention logic, and level shifters – are robustly tested ...