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10.1109/ASYNC.2010.12guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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M-of-N Code Decomposition for Indicating Combinational Logic

Published: 03 May 2010 Publication History

Abstract

Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. In particular, mapping large function blocks into cell-libraries is difficult as decomposing gates introduces new signals which may violate indication. This paper presents a novel method for implementing any m-of-n encoded function block using "bounded gates", where any gate may be decomposed without violating indication. This is achieved by successively decomposing the input encoding into smaller m-of-n codes. The method described in the paper uses algebraic extraction techniques to efficiently determine and quantify potential re-encodings. The results of the synthesis procedure are demonstrated on a range of combinational function blocks.

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Published In

cover image Guide Proceedings
ASYNC '10: Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
May 2010
179 pages
ISBN:9780769540320

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 May 2010

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  1. Asynchronous Combinational Logic Synthesis
  2. M-of-N Codes

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