Article

Ultra-fine grain FPGAs: A granularity study

Authors:

Pierre-Emmanuel Gaillardon,

M. Haykel Ben-Jamaa,

Fabien Clermidy,

Ian O'ConnorAuthors Info & Claims

NANOARCH '11: Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures

Pages 9 - 15

https://doi.org/10.1109/NANOARCH.2011.5941477

Published: 08 June 2011 Publication History

Abstract

In this paper, we investigate the opportunity to use ultra-fine grain logic cells to design reconfigurable circuits. We use ultra-fine grain computation cells, built with only 7 Double-Gate Carbon Nanotubes FETs, and we arrange them into regular matrices with a fixed and incomplete interconnection pattern, in order to minimize the reconfigurable interconnection overhead. We subsequently organize them into Field-Programmable Gate Arrays (FPGAs) suited to ultra-fine grain reconfigurability. To assess this architectural scheme in an efficient and objective manner, we propose a complete benchmarking tool flow, which enables the optimization of the specific interconnection topologies. We finally perform the evaluation with widely used circuit benchmarks, and we show that the matrices have an optimal size of 3 by 3, while the ultra-fine grain FPGA demonstrated an area saving of up to 62% with respect to the CMOS LUT FPGA counterpart.

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Cited By

Bobba SGaillardon PZhang JDe Marchi MSacchetto DLeblebici YDe Micheli GMoritz C(2012)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistorsProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures10.1145/2765491.2765503(55-60)Online publication date: 4-Jul-2012
https://dl.acm.org/doi/10.1145/2765491.2765503

Index Terms

Ultra-fine grain FPGAs: A granularity study
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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cover image ACM Conferences

NANOARCH '11: Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures

June 2011

229 pages

ISBN:9781457709937

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 08 June 2011

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Cited By

Bobba SGaillardon PZhang JDe Marchi MSacchetto DLeblebici YDe Micheli GMoritz C(2012)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistorsProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures10.1145/2765491.2765503(55-60)Online publication date: 4-Jul-2012
https://dl.acm.org/doi/10.1145/2765491.2765503

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