Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices

This paper describes an interconnection scheme and its associated mapping method, used to program complex functions onto reconfigurable architectures, based on nanoscale logic cells. To interconnect such fine-grain logic cells, classical techniques are not suitable because of a large overhead. Therefore, we propose the use of static and incomplete interconnection topologies. We also propose a method to map functions onto such architectures. To evaluate the 4 different proposed topologies, we test mapping efficiency, performances and fault tolerance. The analyses show that this approach could improve the scalability of traditional EPGAs by a factor of 8.