research-article

Software-Hardware Codesign for Efficient Neural Network Acceleration

Authors:

Yu Wang,

Huazhong YangAuthors Info & Claims

IEEE Micro, Volume 37, Issue 2

Pages 18 - 25

https://doi.org/10.1109/MM.2017.39

Published: 01 March 2017 Publication History

Abstract

Designers making deep learning computing more efficient cannot rely solely on hardware. Incorporating software-optimization techniques such as model compression leads to significant power savings and performance improvement. This article provides an overview of DeePhi's technology flow, including compression, compilation, and hardware acceleration. Two accelerators, named Aristotle and Descartes, are designed to achieve extremely high energy efficiency for both client and datacenter applications with convolutional neural network and recurrent neural network, respectively.

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Koshiba AGust FPritzi JVahldiek-Oberwagner ASantos NBhatotia P(2023)Trusted Heterogeneous Disaggregated ArchitecturesProceedings of the 14th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3609510.3609812(72-79)Online publication date: 24-Aug-2023
https://dl.acm.org/doi/10.1145/3609510.3609812
Islam MAlam SUdoy MHossain MAziz AThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)A Cryogenic Artificial Synapse based on Superconducting MemristorProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590203(143-148)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590203
Bravo-Rocca GLiu PGuitart JDholakia AEllison DFalkanger JHodak M(2022)ScanflowExpert Systems with Applications: An International Journal10.1016/j.eswa.2022.117232202:COnline publication date: 15-Sep-2022
https://dl.acm.org/doi/10.1016/j.eswa.2022.117232
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Index Terms

Software-Hardware Codesign for Efficient Neural Network Acceleration
1. Computing methodologies
  1. Machine learning
    1. Machine learning approaches
      1. Neural networks

Index terms have been assigned to the content through auto-classification.

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Information

Published In

IEEE Micro Volume 37, Issue 2

March 2017

102 pages

ISSN:0272-1732

Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 March 2017

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Koshiba AGust FPritzi JVahldiek-Oberwagner ASantos NBhatotia P(2023)Trusted Heterogeneous Disaggregated ArchitecturesProceedings of the 14th ACM SIGOPS Asia-Pacific Workshop on Systems10.1145/3609510.3609812(72-79)Online publication date: 24-Aug-2023
https://dl.acm.org/doi/10.1145/3609510.3609812
Islam MAlam SUdoy MHossain MAziz AThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)A Cryogenic Artificial Synapse based on Superconducting MemristorProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590203(143-148)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590203
Bravo-Rocca GLiu PGuitart JDholakia AEllison DFalkanger JHodak M(2022)ScanflowExpert Systems with Applications: An International Journal10.1016/j.eswa.2022.117232202:COnline publication date: 15-Sep-2022
https://dl.acm.org/doi/10.1016/j.eswa.2022.117232
Zhang YJiang HLiu XCao HDu Y(2022)High-efficient MPSoC-based CNNs accelerator with optimized storage and dataflowThe Journal of Supercomputing10.1007/s11227-021-03909-y78:3(3205-3225)Online publication date: 1-Feb-2022
https://dl.acm.org/doi/10.1007/s11227-021-03909-y
Pham-Quoc CNguyen XThinh T(2022)Towards An FPGA-targeted Hardware/Software Co-design Framework for CNN-based Edge ComputingMobile Networks and Applications10.1007/s11036-022-01985-927:5(2024-2035)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1007/s11036-022-01985-9
Wu CWang MChu XWang KHe L(2021)Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN AccelerationACM Transactions on Reconfigurable Technology and Systems10.1145/347459715:1(1-21)Online publication date: 9-Nov-2021
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Kabir HKhosravi AMondal SRahman MNahavandi SBuyya R(2021)Uncertainty-aware Decisions in Cloud ComputingACM Computing Surveys10.1145/344758354:4(1-30)Online publication date: 24-May-2021
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Ranganathan PStodolsky DCalow JDorfman JGuevara MSmullen IV CKuusela ABalasubramanian RBhatia SChauhan PCheung AChong IDasharathi NFeng JFosco BFoss SGelb BGwin SHase YHe DHo CHuffman Jr. RIndupalli EJayaram IKongetira PKyaw CLaursen ALi YLou FLucke KMaaninen JMacias RMahony MMunday DMuroor SPenukonda NPerkins-Argueta EPersaud DRamirez ARautio VRipley YSalek ASekar SSokolov SSpringer RStark DTan MWachsler MWalton AWickeraad DWijaya AWu HSherwood TBerger EKozyrakis C(2021)Warehouse-scale video acceleration: co-design and deployment in the wildProceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3445814.3446723(600-615)Online publication date: 19-Apr-2021
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Zhang YPan JLiu XChen HChen DZhang ZShannon LAdler M(2021)FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional ActivationsThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439296(171-182)Online publication date: 17-Feb-2021
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Liu BWu QZhang YCao QXu X(2020)Exploiting the Relationship between Pruning Ratio and Compression Effect for Neural Network Model Based on TensorFlowSecurity and Communication Networks10.1155/2020/52186122020Online publication date: 1-Jan-2020
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Hardware/software codesign for embedded implementation of neural networks

Leveraging reconfigurability in the hardware/software codesign process

Convolutional neural network acceleration with hardware/software co-design

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