research-article

SARC Coherence: Scaling Directory Cache Coherence in Performance and Power

Authors:

Stefanos Kaxiras,

Georgios KeramidasAuthors Info & Claims

IEEE Micro, Volume 30, Issue 5

Pages 54 - 65

https://doi.org/10.1109/MM.2010.82

Published: 01 September 2010 Publication History

Publisher Site

Abstract

The SARC project seeks to improve power scalability of shared-memory chip multiprocessors (CMPs) by making directory coherence more efficient in both power and performance. The authors describe how they eliminate two major sources of inefficiency for directory coherence protocols: invalidation traffic on writes and directory indirection for finding the writer.

Cited By

View all

Alsop JNa WSinclair MGrayson SAdve S(2022)A Case for Fine-grain Coherence Specialization in Heterogeneous SystemsACM Transactions on Architecture and Code Optimization10.1145/353081919:3(1-26)Online publication date: 22-Aug-2022
https://dl.acm.org/doi/10.1145/3530819
AlBarakat LGratz PJiménez DAyguadé EHwu WBadia RHofstee H(2020)SB-FetchProceedings of the 34th ACM International Conference on Supercomputing10.1145/3392717.3392735(1-12)Online publication date: 29-Jun-2020
https://dl.acm.org/doi/10.1145/3392717.3392735
Wang MTa TCheng LBatten CMartínez JDuato JEeckhout L(2020)Efficiently supporting dynamic task parallelism on heterogeneous cache-coherent systemsProceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture10.1109/ISCA45697.2020.00025(173-186)Online publication date: 30-May-2020
https://dl.acm.org/doi/10.1109/ISCA45697.2020.00025
Show More Cited By

SARC Coherence: Scaling Directory Cache Coherence in Performance and Power

Recommendations

Proximity-aware directory-based coherence for multi-core processor architectures
SPAA '07: Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures

As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue for multi-core performance. This is exacerbated by the fact that interconnection speeds are not scaling well with technology. This paper describes ...
Temporal-based multilevel correlating inclusive cache replacement

Inclusive caches have been widely used in Chip Multiprocessors (CMPs) to simplify cache coherence. However, they have poor performance compared with noninclusive caches not only because of the limited capacity of the entire cache hierarchy but also due ...
Directory based cache coherence verification logic in CMPs cache system
MES '13: Proceedings of the First International Workshop on Many-core Embedded Systems

This work reports a high speed protocol verificaion logic for Chip Multiprocessors (CMPs) realizing directory based cache coherence system. A special class of cellular automata (CA) referred to as single length cycle 2-attractor CA (TACA), has been ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

IEEE Micro Volume 30, Issue 5

September 2010

105 pages

ISSN:0272-1732

Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 September 2010

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

30
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 19 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Alsop JNa WSinclair MGrayson SAdve S(2022)A Case for Fine-grain Coherence Specialization in Heterogeneous SystemsACM Transactions on Architecture and Code Optimization10.1145/353081919:3(1-26)Online publication date: 22-Aug-2022
https://dl.acm.org/doi/10.1145/3530819
AlBarakat LGratz PJiménez DAyguadé EHwu WBadia RHofstee H(2020)SB-FetchProceedings of the 34th ACM International Conference on Supercomputing10.1145/3392717.3392735(1-12)Online publication date: 29-Jun-2020
https://dl.acm.org/doi/10.1145/3392717.3392735
Wang MTa TCheng LBatten CMartínez JDuato JEeckhout L(2020)Efficiently supporting dynamic task parallelism on heterogeneous cache-coherent systemsProceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture10.1109/ISCA45697.2020.00025(173-186)Online publication date: 30-May-2020
https://dl.acm.org/doi/10.1109/ISCA45697.2020.00025
Jääskeläinen PKorhonen VKoskela MTakala JEgiazarian KDanielyan ACruz CPrice JMcintosh-Smith S(2019)Exploiting Task Parallelism with OpenCLJournal of Signal Processing Systems10.1007/s11265-018-1416-191:1(33-46)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1007/s11265-018-1416-1
Mohr MTradowsky C(2017)PegasusProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130794(1785-1790)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130794
Dublish SNagarajan VTopham N(2016)Cooperative Caching for GPUsACM Transactions on Architecture and Code Optimization10.1145/300158913:4(1-25)Online publication date: 12-Dec-2016
https://dl.acm.org/doi/10.1145/3001589
Yao YWang GGe ZMitra TChen WZhang N(2016)Efficient Timestamp-Based Cache Coherence Protocol for Many-Core ArchitecturesProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926270(1-13)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1145/2925426.2926270
Ros AJimborean A(2016)A Hybrid Static-Dynamic Classification for Dual-Consistency Cache CoherenceIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.252824127:11(3101-3115)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TPDS.2016.2528241
Abdulla PAtig MKaxiras SLeonardsson CRos AZhu Y(2016)Fencing Programs with Self-Invalidation and Self-Downgrade36th IFIP WG 6.1 International Conference on Formal Techniques for Distributed Objects, Components, and Systems - Volume 968810.1007/978-3-319-39570-8_2(19-35)Online publication date: 6-Jun-2016
https://dl.acm.org/doi/10.1007/978-3-319-39570-8_2
Kumar SShriraman AVedula N(2015)FusionACM SIGARCH Computer Architecture News10.1145/2872887.275042143:3S(733-745)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750421
Show More Cited By

Abstract

Cited By

Recommendations

Proximity-aware directory-based coherence for multi-core processor architectures

Temporal-based multilevel correlating inclusive cache replacement

Directory based cache coherence verification logic in CMPs cache system

Comments

Information

Published In

Publisher

Publication History

Author Tags

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations