research-article

A Novel Processor Architecture with Exact Tag-Free Pointers

Author:

Matthias MeyerAuthors Info & Claims

IEEE Micro, Volume 24, Issue 3

Pages 46 - 55

https://doi.org/10.1109/MM.2004.2

Published: 01 May 2004 Publication History

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Abstract

Along with the success of Java, garbage collection advances to embedded and real-time systems. Our novel processor architecture lays the foundation for efficient real-time garbage collection in hardware and guarantees pointer integrity at the machine-code level.

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Cited By

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Jang JHeo JLee YWon JKim SJung SJang HHam TLee J(2019)CharonProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358297(726-739)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358297
Ismail MSuh G(2018)Hardware-software co-optimization of memory management in dynamic languagesACM SIGPLAN Notices10.1145/3299706.321056653:5(45-58)Online publication date: 18-Jun-2018
https://dl.acm.org/doi/10.1145/3299706.3210566
Ismail MSuh GPayer HSartor J(2018)Hardware-software co-optimization of memory management in dynamic languagesProceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management10.1145/3210563.3210566(45-58)Online publication date: 18-Jun-2018
https://dl.acm.org/doi/10.1145/3210563.3210566
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A Novel Processor Architecture with Exact Tag-Free Pointers

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Published In

IEEE Micro Volume 24, Issue 3

May 2004

68 pages

ISSN:0272-1732

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 May 2004

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Jang JHeo JLee YWon JKim SJung SJang HHam TLee J(2019)CharonProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358297(726-739)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358297
Ismail MSuh G(2018)Hardware-software co-optimization of memory management in dynamic languagesACM SIGPLAN Notices10.1145/3299706.321056653:5(45-58)Online publication date: 18-Jun-2018
https://dl.acm.org/doi/10.1145/3299706.3210566
Ismail MSuh GPayer HSartor J(2018)Hardware-software co-optimization of memory management in dynamic languagesProceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management10.1145/3210563.3210566(45-58)Online publication date: 18-Jun-2018
https://dl.acm.org/doi/10.1145/3210563.3210566
Lopriore L(2018)Password-based protection of clustered segments in distributed memory systemsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.01.003115:C(29-40)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1016/j.jpdc.2018.01.003
Nagarakatte SMartin MZdancewic SLu STorrellas J(2012)WatchdogProceedings of the 39th Annual International Symposium on Computer Architecture10.5555/2337159.2337181(189-200)Online publication date: 9-Jun-2012
https://dl.acm.org/doi/10.5555/2337159.2337181
Nagarakatte SMartin MZdancewic S(2012)WatchdogACM SIGARCH Computer Architecture News10.1145/2366231.233718140:3(189-200)Online publication date: 9-Jun-2012
https://dl.acm.org/doi/10.1145/2366231.2337181
Tang JLiu SGu ZLi XGaudiot J(2012)Achieving middleware execution efficiencyThe Journal of Supercomputing10.1007/s11227-010-0493-059:3(1101-1119)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1007/s11227-010-0493-0
Preußer TReichel PSpallek R(2010)An embedded GC module with support for multiple mutators and weak referencesProceedings of the 23rd international conference on Architecture of Computing Systems10.1007/978-3-642-11950-7_4(25-36)Online publication date: 22-Feb-2010
https://dl.acm.org/doi/10.1007/978-3-642-11950-7_4
Joao JMutlu OPatt Y(2009)Flexible reference-counting-based hardware acceleration for garbage collectionACM SIGARCH Computer Architecture News10.1145/1555815.155580637:3(418-428)Online publication date: 20-Jun-2009
https://dl.acm.org/doi/10.1145/1555815.1555806
Joao JMutlu OPatt YKeckler SBarroso L(2009)Flexible reference-counting-based hardware acceleration for garbage collectionProceedings of the 36th annual international symposium on Computer architecture10.1145/1555754.1555806(418-428)Online publication date: 20-Jun-2009
https://dl.acm.org/doi/10.1145/1555754.1555806
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References

Cited By

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The Superthreaded Processor Architecture

A design of EPIC type processor based on MIPS architecture

An Improved Pipelined Processor Architecture Eliminating Branch and Jump Penalty

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