research-article

Hyperthreading Technology in the Netburst Microarchitecture

Authors:

David Koufaty,

Deborah T. MarrAuthors Info & Claims

IEEE Micro, Volume 23, Issue 2

Pages 56 - 65

https://doi.org/10.1109/MM.2003.1196115

Published: 01 March 2003 Publication History

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Abstract

By using existing processor resources more efficiently,hyperthreading technology improves performance at little costand increases chip size by less than 5 percent.

References

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Cited By

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Ji XCheng YZhang JChi YXu WChen Y(2021)Device Fingerprinting with Magnetic Induction Signals Radiated by CPU ModulesACM Transactions on Sensor Networks10.1145/349515818:2(1-28)Online publication date: 21-Dec-2021
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Kanemitsu HKanai KKatto JNakazato H(2021)A containerized task clustering for scheduling workflows to utilize processors and containers on cloudsThe Journal of Supercomputing10.1007/s11227-021-03789-277:11(12879-12923)Online publication date: 1-Nov-2021
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Jia WShan JLi TShang XCui HDing XGavrilovska AZadok E(2020)vSMT-IOProceedings of the 2020 USENIX Conference on Usenix Annual Technical Conference10.5555/3489146.3489176(449-463)Online publication date: 15-Jul-2020
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Index Terms

Hyperthreading Technology in the Netburst Microarchitecture
1. Hardware
  1. Integrated circuits
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management
        Multithreading

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Reviews

Reviewer: Michael Zastre

This is a very good introduction to simultaneous multithreading (SMT), and to Intel's flavor of SMT (hyperthreading) in particular. The paper is roughly divided into three parts. The first motivates the need for SMT. The second part is an overview of Intel's design and implementation of hyperthreading, along with a discussion of the choices and tradeoffs faced by their engineers. The last part provides measures of the performance improvements obtained with hyperthreading. The quality of writing is excellent throughout the paper, and one need not have a background in hardware architecture to grasp the authors' message. Those interested in more detail should be pleased with the authors' description of instruction queues and resource sharing. Online Computing Reviews Service

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Information

Published In

IEEE Micro Volume 23, Issue 2

March 2003

143 pages

ISSN:0272-1732

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Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 March 2003

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Ji XCheng YZhang JChi YXu WChen Y(2021)Device Fingerprinting with Magnetic Induction Signals Radiated by CPU ModulesACM Transactions on Sensor Networks10.1145/349515818:2(1-28)Online publication date: 21-Dec-2021
https://dl.acm.org/doi/10.1145/3495158
Kanemitsu HKanai KKatto JNakazato H(2021)A containerized task clustering for scheduling workflows to utilize processors and containers on cloudsThe Journal of Supercomputing10.1007/s11227-021-03789-277:11(12879-12923)Online publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1007/s11227-021-03789-2
Jia WShan JLi TShang XCui HDing XGavrilovska AZadok E(2020)vSMT-IOProceedings of the 2020 USENIX Conference on Usenix Annual Technical Conference10.5555/3489146.3489176(449-463)Online publication date: 15-Jul-2020
https://dl.acm.org/doi/10.5555/3489146.3489176
Jin XZhou YHuang BYu ZZhan XWang HWang SYu NSun NBao YEigenmann RDing CMcKee S(2019)QoSMTProceedings of the ACM International Conference on Supercomputing10.1145/3330345.3330364(206-216)Online publication date: 26-Jun-2019
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Abstract

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Cited By

Index Terms

Recommendations

Microarchitecture of HaL's CPU

IBM POWER8 processor core microarchitecture

Analyzing the effects of hyperthreading on the performance of data management systems

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