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Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Published: 01 December 2007 Publication History

Abstract

DRAMs require periodic refresh for preserving data stored in them. The refresh interval for DRAMs depends on the vendor and the de- sign technology they use. For each refresh in a DRAM row, the stored information in each cell is read out and then written back to itself as each DRAM bit read is self-destructive. The refresh pro- cess is inevitable for maintaining data correctness, unfortunately, at the expense of power and bandwidth overhead. The future trend to integrate layers of 3D die-stacked DRAMs on top of a proces- sor further exacerbates the situation as accesses to these DRAMs will be more frequent and hiding refresh cycles in the available slack becomes increasingly difficult. Moreover, due to the implica- tion of temperature increase, the refresh interval of 3D die-stacked DRAMs will become shorter than those of conventional ones. This paper proposes an innovative scheme to alleviate the en- ergy consumed in DRAMs. By employing a time-out counter for each memory row of a DRAM module, all the unnecessary periodic refresh operations can be eliminated. The basic concept behind our scheme is that a DRAM row that was recently read or written to by the processor (or other devices that share the same DRAM) does not need to be refreshed again by the periodic refresh opera- tion, thereby eliminating excessive refreshes and the energy dissi- pated. Based on this concept, we propose a low-cost technique in the memory controller for DRAM power reduction. The simulation results show that our technique can reduce up to 86% of all refresh operations and 59.3% on the average for a 2GB DRAM. This in turn results in a 52.6% energy savings for refresh operations. The overall energy saving in the DRAM is up to 25.7% with an average of 12.13% obtained for SPLASH-2, SPECint2000, and Biobench benchmark programs simulated on a 2GB DRAM. For a 64MB 3D DRAM, the energy saving is up to 21% and 9.37% on an average when the refresh rate is 64 ms. For a faster 32ms refresh rate the maximum and average savings are 12% and 6.8% respectively.

Cited By

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  • (2024)PROMPT: A Fast and Extensible Memory Profiling FrameworkProceedings of the ACM on Programming Languages10.1145/36498278:OOPSLA1(449-473)Online publication date: 29-Apr-2024
  • (2021)Modernizing parallel code with pattern analysisProceedings of the 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3437801.3441603(418-430)Online publication date: 17-Feb-2021
  • (2019)Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy RepairACM Transactions on Design Automation of Electronic Systems10.1145/333985124:5(1-31)Online publication date: 10-Jul-2019
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Published In

cover image ACM Conferences
MICRO 40: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
December 2007
435 pages
ISBN:0769530478

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IEEE Computer Society

United States

Publication History

Published: 01 December 2007

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Micro-40
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MICRO 40 Paper Acceptance Rate 35 of 166 submissions, 21%;
Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

View all
  • (2024)PROMPT: A Fast and Extensible Memory Profiling FrameworkProceedings of the ACM on Programming Languages10.1145/36498278:OOPSLA1(449-473)Online publication date: 29-Apr-2024
  • (2021)Modernizing parallel code with pattern analysisProceedings of the 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3437801.3441603(418-430)Online publication date: 17-Feb-2021
  • (2019)Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy RepairACM Transactions on Design Automation of Electronic Systems10.1145/333985124:5(1-31)Online publication date: 10-Jul-2019
  • (2019)CROWProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322231(129-142)Online publication date: 22-Jun-2019
  • (2019)Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisationJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2019.101648100:COnline publication date: 1-Nov-2019
  • (2018)DAREInternational Journal of High Performance Computing Applications10.1177/109434201771861232:1(74-88)Online publication date: 1-Jan-2018
  • (2018)EARProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243182(1-11)Online publication date: 1-Nov-2018
  • (2018)HMCThermProceedings of the International Symposium on Memory Systems10.1145/3240302.3240319(209-117)Online publication date: 1-Oct-2018
  • (2018)A performance & power comparison of modern high-speed DRAM architecturesProceedings of the International Symposium on Memory Systems10.1145/3240302.3240315(341-353)Online publication date: 1-Oct-2018
  • (2018)Reducing DRAM latency via charge-level-aware look-ahead partial restorationProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00032(298-311)Online publication date: 20-Oct-2018
  • Show More Cited By

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