research-article

Design and process variation analysis of CNTFET-based ternary memory cells

Authors:

Fabrizio LombardiAuthors Info & Claims

Integration, the VLSI Journal, Volume 54, Issue C

Pages 97 - 108

https://doi.org/10.1016/j.vlsi.2016.02.003

Published: 01 June 2016 Publication History

Abstract

Two novel ternary CNTFET-based SRAM cells are proposed in this paper. The first proposed CNTFET SRAM uses additional CNTFETs to sink the bit lines to ground; its operation is nearly independent of the ternary values. The second cell utilizes the traditional voltage controller (or supply) of a binary SRAM in a ternary SRAM; it consists of adding two CNTFETs to the first proposed cell. CNTFET features (such as sizing and density) and performance metrics (such as SNM and PDP) and write/read times are considered and assessed in detail. The impact of different features (such as chirality and CNT density) is also analyzed with respect to the operations of the memory cells. The effects of different process variations (such as lithography and density/number of CNTs) are extensively evaluated with respect to performance metrics. In nearly all cases, the proposed cells outperform existing CNTFET-based cells by showing a small standard deviation in the simulated memory circuits. Two novel ternary CNTFET-based SRAM cells are proposed in this paper.

References

[1]

K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, H. Kobatake, A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications, IEEE J. Solid-State Circuits, 41 (2006) 113-121.

[2]

H. Noguchi, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. Kawaguchi, M. Yoshimoto, A 10T non-precharge two-port SRAM for 74% power reduction in video processing, IEEE Computer Society and Annual Symposium VLSI, 2007, pp. 107-112.

Digital Library

[3]

M. Qazi, M.E. Sinangil, A.P. Chandrakasan, Challenges and directions for low-voltage SRAM, IEEE Des. Test Comput., 28 (2011) 32-43.

Digital Library

[4]

P.C. Balla, A. Antoniou, Low power dissipation MOS ternary logic family, IEEE J. Solid-State Circuits, 19 (1984) 739-749.

[5]

J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part i: model of the intrinsic channel region, IEEE Trans. Electron Dev., 54 (2007) 3186-3194.

[6]

J. Deng, H.-S. P.Wong, A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application-Part II: full device model and circuit performance benchmarking, IEEE Trans. Electron Dev., 54 (2007) 3195-3205.

[7]

N. Patil, J. Deng, A. Lin, H.-S.P. Wong, S. Mitra, Design methods for misaligned and mispositioned carbon-nanotube immune circuits, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (2008) 1725-1736.

Digital Library

[8]

N. Patil, J. Deng, S. Mitra, H.-S.P. Wong, Circuit-level performance benchmarking and scalability of carbon nanotube transistor circuits, IEEE Trans. Nanotechnol., 8 (2009) 37-45.

Digital Library

[9]

N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong, S. Mitra, Scalable carbon nanotube computational and storage circuits immune to metallic and mis-positioned carbon nanotubes, IEEE Trans. Nanotechnol., 10 (2011) 744-750.

Digital Library

[10]

G. Cho, Y. Kim, M. Choi, F. Lombardi, Performance evaluation of CNFET-based logic gates, Instruments and Measurement Technology Conference, 2009, pp. 909-912.

[11]

G. Cho, Y. Kim, F. Lombardi, Assessment of the CNFET based circuit performance and robustness to PVT variation, IEEE International Midwest Symposium on Circuits and Systems, 2009, pp. 1106-1109.

[12]

G. Cho, Y. Kim, F. Lombardi, Modeling undeposited CNTs for CNTFET operation, IEEE Trans. Dev. Mater. Reliab., 11 (2011) 263-272.

[13]

A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design, IEEE Trans. Nanotechnol., 4 (2005) 168-179.

Digital Library

[14]

S. Lin, Y. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits, IEEE Trans. Nanotechnol., 10 (2009) 217-225.

Digital Library

[15]

S. Lin, Y. Kim, F. Lombardi, Design of a ternary memory cell using CNTFETs, IEEE Trans. Nanotechnol., 11 (2012) 1019-1025.

Digital Library

[16]

G. Cho, F. Lombardi, Novel and improved design of a ternary CNTFET-based cell, ACM International conference on Great lakes symposium on VLSI, 2013, pp. 131-136.

Digital Library

[17]

S. Lin, Y.-B. Kim, F. Lombardi, Design of a CNTFET-based SRAM cell by dual-chirality selection, IEEE Trans. Nanotechnol., 9 (2010) 30-37.

Digital Library

[18]

A. Chandrakasan, W.J. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE Press, 2000.

Digital Library

[19]

E. Seevinck, F.J. List, J. Lohstroh, Static-noise margin analysis of MOS SRAM cells, IEEE J. Solid-State Circuits, 22 (1987) 748-754.

Cited By

Sharifi Rad RMohammadi Ghanatghestani MHashemipour M(2024)Efficient ATFA design based on CNTFET technology for error–tolerant applicationsCircuits, Systems, and Signal Processing10.1007/s00034-023-02506-z43:2(1119-1143)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1007/s00034-023-02506-z
Mamatov IÖzçelep YKaçar F(2022)CNTFET based voltage differencing current conveyor low power and universal filterAnalog Integrated Circuits and Signal Processing10.1007/s10470-021-01905-z110:1(127-137)Online publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1007/s10470-021-01905-z
Jooq MBozorgmehr AMirzakuchaki S(2021)An ultra-miniature broadband operational transconductance amplifier utilizing 10 nm wrap-gate CNTFET technologyAnalog Integrated Circuits and Signal Processing10.1007/s10470-020-01763-1107:2(423-434)Online publication date: 1-May-2021
https://dl.acm.org/doi/10.1007/s10470-020-01763-1
Show More Cited By

Design and process variation analysis of CNTFET-based ternary memory cells
1. Hardware
  1. Integrated circuits

Recommendations

A novel and improved design of a ternary CNTFET-based cell
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

A novel ternary CNTFET-based SRAM cell is proposed in this paper; the operation of this CNTFET SRAM is nearly independent of the ternary values, therefore it is said to be balanced. Different from previous ternary cells, the proposed cell does not ...
Electrostatically doped tunnel CNTFET model for low-power VLSI circuit design

With advantages such as low sub-threshold swing, low OFF-state current and the ability to attain a higher ON---OFF ratio, the tunnel CNTFET is one of the most comprehensively investigated devices for low-power application. The problems associated with ...
Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore's law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image Integration, the VLSI Journal

Integration, the VLSI Journal Volume 54, Issue C

June 2016

118 pages

ISSN:0167-9260

Issue’s Table of Contents

Copyright © Elsevier B.V.

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 June 2016

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 16 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Sharifi Rad RMohammadi Ghanatghestani MHashemipour M(2024)Efficient ATFA design based on CNTFET technology for error–tolerant applicationsCircuits, Systems, and Signal Processing10.1007/s00034-023-02506-z43:2(1119-1143)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1007/s00034-023-02506-z
Mamatov IÖzçelep YKaçar F(2022)CNTFET based voltage differencing current conveyor low power and universal filterAnalog Integrated Circuits and Signal Processing10.1007/s10470-021-01905-z110:1(127-137)Online publication date: 1-Jan-2022
https://dl.acm.org/doi/10.1007/s10470-021-01905-z
Jooq MBozorgmehr AMirzakuchaki S(2021)An ultra-miniature broadband operational transconductance amplifier utilizing 10 nm wrap-gate CNTFET technologyAnalog Integrated Circuits and Signal Processing10.1007/s10470-020-01763-1107:2(423-434)Online publication date: 1-May-2021
https://dl.acm.org/doi/10.1007/s10470-020-01763-1
Hosseini SEtezadi S(2021)A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in NanoelectronicsCircuits, Systems, and Signal Processing10.1007/s00034-020-01519-240:3(1314-1332)Online publication date: 1-Mar-2021
https://dl.acm.org/doi/10.1007/s00034-020-01519-2
Takbiri MFaghih Mirzaee RNavi K(2019)Analytical Review of Noise Margin in MVL: Clarification of a Deceptive MatterCircuits, Systems, and Signal Processing10.1007/s00034-019-01063-838:9(4280-4301)Online publication date: 1-Sep-2019
https://dl.acm.org/doi/10.1007/s00034-019-01063-8
Bastani NMoaiyeri MNavi K(2018)An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching LogicCircuits, Systems, and Signal Processing10.1007/s00034-017-0627-137:5(1863-1883)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1007/s00034-017-0627-1
Abiri EDarabi A(2016)A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnologyMicroelectronics Journal10.1016/j.mejo.2016.10.00958:C(44-59)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1016/j.mejo.2016.10.009

View Options

View options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents