Nothing Special   »   [go: up one dir, main page]

skip to main content
research-article

Application performance prediction method based on cross-core performance interference on multi-core processor

Published: 01 November 2016 Publication History

Abstract

Due to the contention for shared resource, applications deployed on different cores would suffer from the performance interference. Therefore, how to predict applications performance reasonably has become the hotspot in current studies. A challenges of the existing application performance prediction methods are hard to determine the pressure indicators and assess the pressure of the multi-interference application forcing, this paper proposes an application performance prediction method which is based on the cross-core performance interference on multi-core processors. In particular, we firstly analyze the relationship between the cross-core shared resource usage and the performance degradation of applications. Then, we- select the appropriate indicators to represent the pressure on shared resources using the correlation analysis, and establish the correlation model between the degree of the performance degradation and the pressure level by using the stepwise regression analysis method. Meanwhile, we consider the mutual of the interference and employ a K-means clustering algorithm to decrease the prediction cost. Experimental results show that the pressure indicators could measure the competition to the resource and the performance model could predict the performance degradation accurately.

References

[1]
Y.C. Ma, W.S. Chao, T.A. Liu, Enabling energy-proportional computing on instruction-level parallel processors, J. Supercomput., 71 (2014) 391-447.
[2]
T. Wood, P. Shenoy, A. Venkataramani, M. Yousif, Sandpiper: black-box and gray-box resource management for virtual machines, Comput. Netw., 53 (2009) 2923-2938.
[3]
J. Zhao, H. Cui, X. Feng, Analyzing cross-core performance interference on multi-core processors based on statistical learning, J. Softw., 24 (2013) 2558-2570.
[4]
J. Mars, L. Tang, R. Hundt, K. Skadron, M.L. Soffa, Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations, in: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011, pp. 248-259.
[5]
L. Lei, A. Huiyao, Z. Peng, Study on last-level cache management strategy of the chip multi-processor, Appl. Math, 9 (2015) 661-670.
[6]
M. Kharbutli, M. Jarrah, Y. Jararweh, SCIP: Selective cache insertion and bypassing to improve the performance of last-level caches, in: Proceedings of 2013 IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT), 2013, pp. 1-6.
[7]
L.M. Pinho, E. Quinones, M. Bertogna, A. Marongiu, J. Pereira Carlos, C. Scordino, P-SOCRATES: a Parallel Software Framework for Time-Critical Many-Core Systems, in: Proceedings of 2014 17th Euro Micro Conference on Digital System Design (DSD), 2014, pp. 214-221.
[8]
F.N. Sibai, On the performance benefits of sharing and privatizing second and third-level cache memories in homogeneous multi-core architectures, Microprocess. Microsyst., 32 (2008) 405-412.
[9]
S. Trujillo, A. Crespo, A. Alonso, J. Prez, MultiPARTES: Multi-core partitioning and virtualization for easing the certification of mixed-criticality systems, Microprocess. Microsyst., 38 (2014) 921-932.
[10]
C. Delimitrou, C. Kozyrakis, Paragon: QoS-aware scheduling for heterogeneous datacenters, ACM SIGARCH Comput. Archit. News, 41 (2013) 77-88.
[11]
S. Govindan, J. Liu, A. Kansal, A. Sivasubramaniam, Cuanta: quantifying effects of shared on-chip resource interference for consolidated virtual machines, in: Proceedings of Symposium on Cloud Computing, 2011.
[12]
R.C. Chiang, H.H. Huang, TRACON: Interference-aware scheduling for data-intensive applications in virtualized environments, IEEE Trans. Parallel Distrib. Syst., 25 (2011) 1349-1358.
[13]
Z. Wang, M.F. O'Boyle, Mapping parallelism to multi-cores: a machine learning based approach, in: ACM Sigplan Notices, 2009, pp. 75-84.
[14]
J. Mars, L. Tang, M.L. Soffa, Directly characterizing cross core interference through contention synthesis, in: Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers, 2011, pp. 167-176.
[15]
S. Borkar, A.A. Chien, The future of microprocessors, Commun. ACM, 54 (2011) 67-77.
[16]
P. Hammarlund, R. Kumar, R.B. Osborne, R. Rajwar, R. Singhal, R. D'Sa, Haswell: The fourth-generation Intel core processor, in: IEEE Micro, 2014, pp. 6-20.
[17]
S. Prabhu, R. Daruwala, Measuring performance degradation in multi-core processors due to shared resources, Int. J. Eng. Res. Appl., 3 (2012) 98-102.
[18]
S. Khan, A.R. Alameldeen, C. Wilkerson, O. Mutlu, D.A. Jimnez, Improving cache performance by exploiting read-write disparity, in: Proceedings of the 20th International Symposium on High Performance Computer Architecture (HPCA), 2014, pp. 1-12.
[19]
L. Soares, D. Tam, M. Stumm, Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer, in: Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, 2008, pp. 258-269.
[20]
Y. Koh, R. Knauerhase, P. Brett, M. Bowman, Z. Wen, C. Pu, An analysis of performance interference effects in virtual environments, in: Proceedings of IEEE International Symposium on Performance Analysis of Systems & Software, 2007. ISPASS 2007, 2007, pp. 200-209.
[21]
R. Nathuji, A. Kansal, A. Ghaffarkhah, Q-clouds: managing performance interference effects for qos-aware clouds, in: Proceedings of the 5th European Conference on Computer Systems, 2010, pp. 237-250.
[22]
Q. Zhu, T. Tung, A performance interference model for managing consolidated workloads in QoS-aware clouds, in: Proceedings of 2012 IEEE 5th International Conference on Cloud Computing (CLOUD), 2012, pp. 170-179.
[23]
L. Tang, J. Mars, M.L. Soffa, Contentiousness vs. sensitivity: improving contention aware runtime systems on multicore architectures, in: Proceedings of the 1st International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era, 2011, pp. 12-21.
[24]
J. Mars, L. Tang, Chapter 2 - understanding application contentiousness and sensitivity on modern multicores, in: Advances in Computers, 2013, pp. 59-85.
[25]
Y. Jiang, X. Shen, J. Chen, R. Tripathi, Analysis and approximation of optimal co-scheduling on chip multiprocessors, in: Proceedings of the 17th International Conference On Parallel Architectures and Compilation Techniques, 2008, pp. 220-229.
[26]
L. Tang, J. Mars, X. Zhang, R. Hagmann, R. Hundt, E. Tune, Optimizing Google's warehouse scale computers: the NUMA experience, in: Proceedings of 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA2013), 2013, pp. 188-197.
[27]
L. Tang, J. Mars, N. Vachharajani, R. Hundt, M.L. Soffa, The impact of memory subsystem resource sharing on datacenter applications, in: Proceedings of 2011 38th Annual International Symposium on Computer Architecture (ISCA), 2011, pp. 283-294.
[28]
J. Zhao, H. Cui, J. Xue, X. Feng, Y. Yan, W. Yang, An empirical model for predicting cross-core performance interference on multicore processors, in: Proceedings of the 22nd international conference on Parallel architectures and compilation techniques, 2013, pp. 201-212.
[29]
T. Dwyer, A. Fedorova, S. Blagodurov, M. Roth, F. Gaud, J. Pei, A practical method for estimating performance degradation on multicore processors, and its application to HPC workloads, in: Proceedings of 2012 International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2012, pp. 1-11.
[30]
S. Verboven, K. Vanmechelen, J. Broeckhove, Black box scheduling for resource intensive virtual machine workloads with interference models, Future Gener. Comput. Syst., 29 (2013) 1871-1884.
[31]
E.Z. Zhang, Y. Jiang, X. Shen, Does Cache Sharing on Modern CMP Matter to the performance of contemporary multithreaded programs?, Acm Sigplan Not., 45 (2010) 203-212.

Cited By

View all
  • (2023)Two-stage scheduling for a fluctuant big data stream on heterogeneous servers with multicores in a data centerCluster Computing10.1007/s10586-023-04044-427:2(1581-1597)Online publication date: 31-May-2023
  • (2016)Special Issue on Real-Time Scheduling on Heterogeneous Multi-core ProcessorsMicroprocessors & Microsystems10.1016/j.micpro.2016.11.00547:PA(90-92)Online publication date: 1-Nov-2016
  1. Application performance prediction method based on cross-core performance interference on multi-core processor

      Recommendations

      Comments

      Please enable JavaScript to view thecomments powered by Disqus.

      Information & Contributors

      Information

      Published In

      cover image Microprocessors & Microsystems
      Microprocessors & Microsystems  Volume 47, Issue PA
      November 2016
      250 pages

      Publisher

      Elsevier Science Publishers B. V.

      Netherlands

      Publication History

      Published: 01 November 2016

      Author Tags

      1. Application performance prediction
      2. Data center
      3. Interference
      4. Multi-core

      Qualifiers

      • Research-article

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)0
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 07 Mar 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2023)Two-stage scheduling for a fluctuant big data stream on heterogeneous servers with multicores in a data centerCluster Computing10.1007/s10586-023-04044-427:2(1581-1597)Online publication date: 31-May-2023
      • (2016)Special Issue on Real-Time Scheduling on Heterogeneous Multi-core ProcessorsMicroprocessors & Microsystems10.1016/j.micpro.2016.11.00547:PA(90-92)Online publication date: 1-Nov-2016

      View Options

      View options

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media