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Conjugate conflict continuation graphs for multi-layer constrained via minimization

Published: 20 June 2007 Publication History

Abstract

A graph model for describing the relationships among wire segments is crucial to constrained via minimization (CVM) in a VLSI design. In this paper we present a new graph model, called the conjugate conflict continuation graph, for multi-layer CVM with stacked vias. This graph model eases the handling of stacked via problems. An integer linear programming (ILP) formulation and a simulated annealing (SA) algorithm based on this graph model are developed to solve multi-layer CVM. The ILP model is too complicated to solve efficiently. The SA algorithm on average achieves 6.4% via reduction for layouts obtained using a commercial tool under a set of practical constraints in which the metal wires (including pins) used in cell layouts, power rails and rings, and clock routing are treated as obstacles or fixed-layer objects to a multi-layer CVM.

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Published In

cover image Information Sciences: an International Journal
Information Sciences: an International Journal  Volume 177, Issue 12
June, 2007
219 pages

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Elsevier Science Inc.

United States

Publication History

Published: 20 June 2007

Author Tags

  1. Graph coloring
  2. Layer assignment
  3. Routing
  4. VLSI
  5. Via minimization

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