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The Via Minimization Problem is NP-Complete

Published: 01 November 1989 Publication History

Abstract

The authors analyze the computational complexity of the constrained via minimization problem. Given an already routed circuit, the problem is to find a minimum cardinality set of vias for which a valid layer assignment exists using only two layers. The authors first prove that the corresponding decision problem is NP-complete. They then show that it remains NP-complete even if one or more of the following restrictions are imposed: (1) the input layout must conform to a rectangular grid; (2) vias are restricted to lie at junctions which existed in the input layout; and (3) the maximum junction degree is limited to six or more.

References

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{1} K. C. Chang and D. H-C. Du, "Efficient algorithms for layer assignment problem," IEEE Trans. Comput.-Aided Design, vol. CAD-6, no. 1, pp. 67-78, Jan. 1987.
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{2} R-W. Chen, Y. Kajitani, and S-P. Chan, "A graph-theoretic via minimization algorithm for two-layer primed circuit boards," IEEE Trans. Circuits Syst., vol. CAS-30, no. 5, pp. 284-299, May 1983.
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{3} N. Chiba, T. Nishizeki, S. Abe, and T. Ozawa, "A linear time algorithm for embedding planar graphs using PQ-trees," J. Comput. Syst. Sci., vol. 30, pp. 54-76, 1985.
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{7} M. R. Garey, D. S. Johnson, and L. Stockmeyer, "Some simplified NP-complete graph problems," Theoret. Comput. Sci., vol. 1, pp. 237-267, 1976.
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{8} M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
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{9} A. Hashimoto and J. Stevens, "Wire routing by optimizing channel assignment within large apertures," in Proc. 8th Design Automat. Workshop, Atlantic City, NJ, June 1971, pp. 155-169.
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{10} C.-P. Hsu, "Minimum via topological routing," IEEE Trans. Comput.-Aided Design, vol. CAD-2, no. 4, pp. 235-246, Oct. 1983.
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{14} N. J. Naclerio, S. Masuda, and K. Nakajima, "Via minimization for gridless layouts," in Proc. 24th Design Automat. Conf., Miami Beach, FL, June 1987, pp. 159-165.
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{15} R. Y. Pinter, "Optimal layer assignment for interconnect," in Proc. 1982 IEEE Int. Conf. Circuits Comput., New York, NY, Sept. 1982, pp. 398-401.
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{16} K. R. Stevens and W. M. VanCleemput, "Global via elimination in generalized routing environment," in Proc. IEEE 1979 Int. Symp. Circuits Syst., Tokyo, Japan, June 1979, pp. 689-692.
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{17} R. Tamassia, "On embedding a graph in the grid with the minimum number of bends," SIAM J. Comput., vol. 16, no. 3, pp. 421-444, June 1987.

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Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 38, Issue 11
November 1989
136 pages
ISSN:0018-9340
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IEEE Computer Society

United States

Publication History

Published: 01 November 1989

Author Tags

  1. NP-complete
  2. circuit layout CAD
  3. computational complexity
  4. constrained via minimization
  5. input layout
  6. minimisation of switching nets.
  7. minimum cardinality set
  8. rectangular grid
  9. valid layer assignment

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  • (2005)An adaptive genetic algorithm for the minimal switching graph problemProceedings of the 5th European conference on Evolutionary Computation in Combinatorial Optimization10.1007/978-3-540-31996-2_21(224-233)Online publication date: 30-Mar-2005
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