An all-digital DLL with duty-cycle correction using reusable TDC
Pages 1055 - 1070
Abstract
This paper presents the design of an all-digital delay-locked loop ADDLL with duty-cycle correction using reusable time-to-digital converter TDC. The proposed ADDLL uses a reusable TDC for achieving a wide-operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18-µm complementary metal-oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50±1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900MHz without frequency doubling. The acceptable input frequency range is from 150 to 450MHz when using frequency doubling. It dissipates 6.2mW from a 1.8-V supply at 900MHz. The peak-to-peak and RMS jitters at 900MHz are 14 and 1.8ps, respectively. Copyright © 2015 John Wiley & Sons, Ltd.
References
[1]
Moon Y, Choi J, Lee K, Jeong D, Kim M. An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE Journal of Solid-State Circuits 2000; Volume 35 Issue 3: pp.377-384.
[2]
Chang H, Lin J, Yang C, Liu S. A wide range delay-locked loop with a fixed latency of one clock cycle. IEEE Journal of Solid-State Circuits 2002; Volume 37: pp.1021-1027.
[3]
Liao F, Lu S. A programmable edge-combining DLL with a current-splitting charge pump for spur suppression. IEEE Trans. Circuits and Systems II: Express Briefs 2010; Volume 57 Issue 12: pp.946-950.
[4]
Jasielski J, Kuta S, Machowski W, Kolodziejski W. An Analog Dual Delay Locked Loop Using Coarse and Fine Programmable Delay Elements. In Proceedings of the 20th International Mixed Design of Integrated Circuits and Systems MIXDES, Gdynia, 2013; pp.185-190.
[5]
Chang H, Liu S. A wide-range and fast-locking all-digital cycle-controlled delay-locked loop. IEEE Journal of Solid-State Circuits 2005; Volume 40 Issue 3: pp.661-670.
[6]
Wang L, Liu L, Chen H. An implementation of fast-locking and wide-range 11-bit reversible SAR DLL. IEEE Trans. Circuits and Systems II: Express Briefs 2010; Volume 57 Issue 6: pp.421-425.
[7]
Shin D, Song J, Chae H, Kim C. A 7 ps jitter 0.053 mm2 fast lock all-digital DLL with a wide range and high resolution DCC. IEEE Journal of Solid-State Circuits 2009; Volume 44 Issue 9: pp.2437-2451.
[8]
Hoyos S, Tsang C, Vanderhaegen J, Chiu Y, Aibara Y, Khorramabadi H, Nikolic B. A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 split-control, fast coarse locking digital DLL in 0.13 m CMOS. IEEE Transactions on Very Large Scale Integration VLSI Systems 2012; Volume 20 Issue 3: pp.564-568.
[9]
Song E, Lee S, Lee J, Park J, Chae S. A reset-free anti-harmonic delay-locked loop using a cycle period detector. IEEE Journal of Solid-State Circuits 2004; Volume 39 Issue 11: pp.2055-2061.
[10]
Dehng G, Lin J, Liu S. A fast-lock mixed-mode DLL using a 2-b SAR algorithm. IEEE Journal of Solid-State Circuits 2004; Volume 36 Issue 10: pp.1464-1471.
[11]
Wang Y, Wang J. An Ultra-Low-Power Fast-Lock-In Small Jitter All-Digital DLL. In IEEE International Solid-State Circuits Conference ISSCC, Digest of Technical Papers, San Francisco, CA, 2005; pp.422-423.
[12]
Cheng K, Lo Y. A fast-lock wide-range delay-locked loop using frequency-range selector for multiphase clock generator. IEEE Trans. Circuits and Systems II: Express Briefs 2007; Volume 54 Issue 6: pp.561-565.
[13]
Yang S, Huang D, Wen X, Chen L, Chen J. A Radiation-Hardened DLL with Fine Resolution and DCC for DDR2 Memory Interface in 0.13µm CMOS. In IEEE International Symposium on Circuits and Systems ISCAS, Beijing, 2013; pp.1496-1499.
[14]
Jung DH, Ryu K, Park JH, Jung SO. A Low-Power and Small-Area All-Digital Delay-Locked Loop with Closed-Loop Duty-Cycle Correction. In Proceedings of the European Solid-State Circuits Conference ESSCIRC, Bordeaux, 2012; pp.181-184.
[15]
Chung C, Sheng D, Shen S. High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology. IEEE Transactions on Very Large Scale Integration VLSI Systems 2014; Volume 22 Issue 5: pp.1096-1105.
[16]
Chen Y, Tsao H, Hwang C. A fast-locking all-digital deskew buffer with duty-cycle correction. IEEE Transactions on Very Large Scale Integration VLSI Systems 2013; Volume 21 Issue 2: pp.270-280.
[17]
Ok S, Chung K, Koo J, Kim C. An antiharmonic, programmable, DLL-based frequency multiplier for dynamic frequency scaling. IEEE Transactions on Very Large Scale Integration VLSI Systems 2010; Volume 18 Issue 7: pp.1130-1134.
[18]
Kuo K, Hsu Y. A 120-420MHz delay-locked loop with multi-band voltage-controlled delay unit. International Journal of Circuit Theory and Applications 2012; Volume 40: pp.49-63.
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Published: 01 May 2016
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