Article

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design

Authors:

Young-Taek Kim,

Eui-Young Chung,

Kyu-Myung Choi,

Jeong-Taek Kong,

Soo-Kwan EoAuthors Info & Claims

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 1

Page 10352

Published: 16 February 2004 Publication History

Abstract

For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approachwith which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.

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Cited By

Medardoni SRuggiero MBertozzi DBenini LStrano GPistritto CLauwereins RMadsen J(2007)Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platformsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266505(660-665)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266505
Chen YTang SLo SCho YWainwright RHaddad HShin SKoo Y(2007)A priority assignment strategy of processing elements over an on-chip busProceedings of the 2007 ACM symposium on Applied computing10.1145/1244002.1244257(1176-1180)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1244002.1244257
Pasricha SDutt NBen-Romdhane MTang T(2005)Automated throughput-driven synthesis of bus-based communication architecturesProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120920(495-498)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120920
Show More Cited By

Index Terms

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
1. Hardware

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Published In

cover image ACM Conferences

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 1

February 2004

688 pages

ISBN:0769520855

Copyright © Copyright (c) 2004 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

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Published: 16 February 2004

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DATE04: Design, Automation and Test in Europe 2004

February 16 - 20, 2004

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Cited By

Medardoni SRuggiero MBertozzi DBenini LStrano GPistritto CLauwereins RMadsen J(2007)Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platformsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266505(660-665)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266505
Chen YTang SLo SCho YWainwright RHaddad HShin SKoo Y(2007)A priority assignment strategy of processing elements over an on-chip busProceedings of the 2007 ACM symposium on Applied computing10.1145/1244002.1244257(1176-1180)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1244002.1244257
Pasricha SDutt NBen-Romdhane MTang T(2005)Automated throughput-driven synthesis of bus-based communication architecturesProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120920(495-498)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120920
Pasricha SDutt NBozorgzadeh EBen-Romdhane MJoyner WMartin GKahng A(2005)Floorplan-aware automated synthesis of bus-based communication architecturesProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065727(565-570)Online publication date: 13-Jun-2005
https://dl.acm.org/doi/10.1145/1065579.1065727

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