Formal verification of an IBM CoreConnect processor local bus arbiter core
A Goel, WR Lee - Proceedings of the 37th Annual Design Automation …, 2000 - dl.acm.org
A Goel, WR Lee
Proceedings of the 37th Annual Design Automation Conference, 2000•dl.acm.orgThis paper describes the model checking effort for an arbiter core for the IBM CoreConnect
Architecture. We present our verification methodology and describe how it was influenced by
the architecture. We also present and analyze the bugs found and discuss the difficulties
associated with verifying complex on-chip buses, highlighting the need for better tools and
methodologies for their specification and verification.
Architecture. We present our verification methodology and describe how it was influenced by
the architecture. We also present and analyze the bugs found and discuss the difficulties
associated with verifying complex on-chip buses, highlighting the need for better tools and
methodologies for their specification and verification.
This paper describes the model checking effort for an arbiter core for the IBM CoreConnect Architecture. We present our verification methodology and describe how it was influenced by the architecture. We also present and analyze the bugs found and discuss the difficulties associated with verifying complex on-chip buses, highlighting the need for better tools and methodologies for their specification and verification.