On-chip networks: A scalable, communication-centric embedded system design paradigm

As chip complexity grows, design productivity boost is expectedfrom reuse of large parts and blocks of previous designswith the design effort largely invested into the new parts.More and more processor cores and large, reusable componentsare being integrated on a single silicon die but reuseof the communication infrastructure has been difficult. Busesand point to point connections, that have been the main meansto connect components on a chip today, will not result in ascalable platform architecture for the billion transistor chipera. Buses can cost efficiently connect a few tens of components.Point to point connections between communicationpartners is practical for even fewer components. As more andmore components are integrated on a single silicon die, performancebottlenecks of long, global wires preclude reuse ofbuses. Therefore, scalable on-chip communication infrastructureis playing an increasingly dominant role in system-on-chipdesigns. With the super-abundance of cheap, function-specificIP cores, design effort will focus on the weakest link:efficient on-chip communication.Future on-chip communication infrastructure will overcomethe limits of bus-based systems by providing higher bandwidth,higher flexibility and by solving the clock skew problemon large chips. It may, however, present new problems:higher power consumption of the communication infrastructureand harder-to-predict performance patterns. Solutionsto these problems may result in a complete overhaul of SOCdesign methodologies into a communication-centric designstyle. The envisioning of upcoming problems and possiblebenefits has led to intensified research in the field of what iscalled NoCs: Networks on Chips. The term NoCs is used in abroad meaning, encompassing the hardware communicationinfrastructure, the middleware and operating system communicationservices, and a design methodology and tools to mapapplications onto a network on chip. This paper discussestrends in system-on-chip designs, critiques problems and opportunitiesof the NoC paradigm, summarizes research activities,and outlines several directions for future research.