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Relax: A new circuit for large scale MOS integrated circuits

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E. Lelarasmee,

A. Sangiovanni-VincentelliAuthors Info & Claims

DAC '82: Proceedings of the 19th Design Automation Conference

Pages 682 - 687

Published: 01 January 1982 Publication History

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Abstract

Algorithms and techniques used in RELAX are described. RELAX is a time domain MOS digital circuit simulator based on a new analysis method called Waveform Relaxation Method [1] which exploits decomposition techniques. Preliminary comparisons between RELAX and the standard circuit simulator SPICE2 have shown that RELAX is a fast and reliable circuit simulator.

References

[1]

E. Lelarasmee, A.E. Ruehli and A.L. Sangiovanni- Vincentelli, "The Waveform Relaxation Method for time domain analysis of large scale integrated circuits," University of California, Berkeley, Electronics Research Laboratory, Memorandum No. UCB/ERI. M81/75, June 1981.

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L.N. Nagel, "SPICE2: A computer program to simulate semiconductor circuits," University of California, Berkeley, Electronics Research Laboratory, Memorandum No. ERL-M520, May 1975.

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A.R, Newton, "The simulation of large scale, integrated circuits," IEEE Trans. on Circuits and Systems, Vol. CAS-26. pp 741-749. September 1979.

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Cited By

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Yu MAckland BJess JRudell R(1994)VLSI timing simulation with selective dynamic regionizationProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191405(195-199)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191405
Stein ANguyen TGeorge BRohrer RNewton A(1991)ADAPTSProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127618(26-31)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127618
Ousterhout J(1988)Switch-level delay models for digital MOS VLSIPapers on Twenty-five years of electronic design automation10.1145/62882.62941(489-495)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/62882.62941
Show More Cited By

Index Terms

Relax: A new circuit for large scale MOS integrated circuits
1. Hardware

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DAC '82: Proceedings of the 19th Design Automation Conference

January 1982

919 pages

ISBN:0897910206

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Published: 01 January 1982

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Yu MAckland BJess JRudell R(1994)VLSI timing simulation with selective dynamic regionizationProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191405(195-199)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191405
Stein ANguyen TGeorge BRohrer RNewton A(1991)ADAPTSProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127618(26-31)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127618
Ousterhout J(1988)Switch-level delay models for digital MOS VLSIPapers on Twenty-five years of electronic design automation10.1145/62882.62941(489-495)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/62882.62941
Beckett WThomas D(1986)MOS circuit models in Network CProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318041(171-178)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318041
Hennion BSenn PCoquelle DOfek HO'Neill L(1985)A new algorithm for third generation circuit simulatorsProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317847(137-143)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317847
Ousterhout JLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)Switch-level delay models for digital MOS VLSIProceedings of the 21st Design Automation Conference10.5555/800033.800851(542-548)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800851
Kao WMovahed-Ezazi MSabiers MLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)ARIESProceedings of the 21st Design Automation Conference10.5555/800033.800812(301-307)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800812

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Abstract

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Cited By

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Recommendations

Relax-and-retime: a methodology for energy-efficient recovery based design

RELAX NG

Optimized reversible binary-coded decimal adders

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