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Custom VLSI electrical rule checking in an intelligent terminal

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L. V. CorbinAuthors Info & Claims

DAC '81: Proceedings of the 18th Design Automation Conference

Pages 696 - 701

Published: 29 June 1981 Publication History

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Abstract

An extension to a language-based custom VLSI design approach is proposed in which the designer supplies just enough up-front semantic information to allow a substantial amount of beneficial design consistency checking with a minimum of computation. The computational load is reduced by using a bottom-up hierarchical design approach, with incremental checking as the design is built. The load is also reduced by imposing minor restrictions upon the layout designer, by requiring that all active elements be prechecked, and by attaching “type” attributes to interconnecting signals. The method is very efficient for highly “regular” designs. Checks performed are geometrical design rules, connectivity, static electrical consistency, and node rise-and-fall times.

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Cited By

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Wagner TLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)Hierarchical layout verificationProceedings of the 21st Design Automation Conference10.5555/800033.800843(484-489)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800843
Lipton RSedgewick RValdes JDeMillo R(1982)Programming aspects of VLSIProceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages10.1145/582153.582160(57-65)Online publication date: 25-Jan-1982
https://dl.acm.org/doi/10.1145/582153.582160

Index Terms

Custom VLSI electrical rule checking in an intelligent terminal
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Very large scale integration design

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DAC '81: Proceedings of the 18th Design Automation Conference

June 1981

899 pages

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IEEE Press

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Published: 29 June 1981

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Wagner TLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)Hierarchical layout verificationProceedings of the 21st Design Automation Conference10.5555/800033.800843(484-489)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800843
Lipton RSedgewick RValdes JDeMillo R(1982)Programming aspects of VLSIProceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages10.1145/582153.582160(57-65)Online publication date: 25-Jan-1982
https://dl.acm.org/doi/10.1145/582153.582160

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An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking

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