Delay Testing with Clock Control: An Alternative to Enhanced Scan
Abstract
Path delay fault testing in non-scan sequential circuits iscomplicated by the limited state transitions during normaloperation. An accepted method for overcoming this difficultyis to use a scan chain consisting of enhanced scan flip-flops,which makes the application of arbitrary vector pairspossible. However, the method results in increased pathdelays because of the enhanced scan flip-flops themselves.In this paper, we present a new method for improving pathdelay fault testability without increasing path delays in thecircuit. It uses a simple clock control circuit to producesingle bit transitions on state variables and a parity checkcircuit for observing state variable flip-flops. The areaoverhead of this method is comparable to enhanced scanbut no performance penalty is incurred. We demonstratethe effectiveness of this method in delay testing and showhow it can be used for stuck-at fault testing as well.
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- Delay Testing with Clock Control: An Alternative to Enhanced Scan
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Published In
November 1997
ISBN:0780342100
Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Publisher
IEEE Computer Society
United States
Publication History
Published: 01 November 1997
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