Article

Statistical Timing Analysis of Combinational Circuits

Authors:

Srinivas Devadas,

Horng-Fei Jyu,

Kurt Keutzer,

Sharad MalikAuthors Info & Claims

ICCD '92: Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors

Pages 38 - 43

Published: 11 October 1992 Publication History

Abstract

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Yang SWang WHagan MZhang WGupta PCao Y(2013)NBTI-aware circuit node criticality computationACM Journal on Emerging Technologies in Computing Systems10.1145/24916819:3(1-19)Online publication date: 8-Oct-2013
https://dl.acm.org/doi/10.1145/2491681
Kaneko MInoue KAtienza DXie YAyala JStevens K(2011)Ordered coloring-based resource binding for datapaths with improved skew-adjustabilityProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973070(307-312)Online publication date: 2-May-2011
https://dl.acm.org/doi/10.1145/1973009.1973070
Mahalingam VRanganathan NHarlow J(2008)A fuzzy optimization approach for variation aware power minimization during gate sizingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515827.151583116:8(975-984)Online publication date: 1-Aug-2008
https://dl.acm.org/doi/10.5555/1515827.1515831
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Statistical Timing Analysis of Combinational Circuits

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Design of Parity Testable Combinational Circuits

The parity testability of a single output is related to its partition in terms of maximal supergates, and a scheme is proposed for making an untestable circuit parity testable by augmenting its maximal supergates. Only a small amount of extra logic and ...

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ICCD '92: Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors

October 1992

534 pages

ISBN:0818631104

Publisher

IEEE Computer Society

United States

Publication History

Published: 11 October 1992

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Yang SWang WHagan MZhang WGupta PCao Y(2013)NBTI-aware circuit node criticality computationACM Journal on Emerging Technologies in Computing Systems10.1145/24916819:3(1-19)Online publication date: 8-Oct-2013
https://dl.acm.org/doi/10.1145/2491681
Kaneko MInoue KAtienza DXie YAyala JStevens K(2011)Ordered coloring-based resource binding for datapaths with improved skew-adjustabilityProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973070(307-312)Online publication date: 2-May-2011
https://dl.acm.org/doi/10.1145/1973009.1973070
Mahalingam VRanganathan NHarlow J(2008)A fuzzy optimization approach for variation aware power minimization during gate sizingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515827.151583116:8(975-984)Online publication date: 1-Aug-2008
https://dl.acm.org/doi/10.5555/1515827.1515831
Wang FWu XXie YKyung CChoi KHa S(2008)Variability-driven module selection with joint design time optimization and post-silicon tuningProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356806(2-9)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356806
Mangassarian HAnis M(2005)On Statistical Timing Analysis with Inter- and Intra-Die VariationsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.226(132-137)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.226
Neiroukh OSong X(2005)Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical TechniquesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.180(294-299)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.180
Agarwal ABlaauw DZolotov V(2003)Statistical Timing Analysis for Intra-Die Process Variations with Spatial CorrelationsProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009993Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009993
Devgan AKashyap C(2003)Block-based Static Timing Analysis with UncertaintyProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009952Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009952
Agarwal ABlaauw DZolotov VVrudhula S(2003)Statistical Timing Analysis Using BoundsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022706Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022706
Agarwal ABlaauw DZolotov VVrudhula SGetreu IFix LLavagno L(2003)Computation and Refinement of Statistical Bounds on Circuit DelayProceedings of the 40th annual Design Automation Conference10.1145/775832.775922(348-353)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.775922
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Quaternary CMOS Combinational Logic Circuits

Design of Memristor-Based Combinational Logic Circuits

Design of Parity Testable Combinational Circuits

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