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Abetting planned obsolescence by aging 3D networks-on-chip

Published: 04 October 2018 Publication History

Abstract

We set up a security analysis framework by aging the Network-on-Chip (NoC) to study planned obsolescence by the original equipment manufacturer (OEM). An NoC is the communication backbone in a manycore System-on-Chip (SoC). Planned obsolescence may adopt any vulnerability in the NoC to cause the SoC to fail. We show how an OEM can craft workloads to generate electromigration-induced stress and crosstalk noise in TSV-based vertical links in the NoC to hasten failure. We analyzed three malicious workloads and confirm that a crafted workload that injects 3--10% more traffic on to a few selected critical vertical links can shorten the lifetime of the NoC by 11%-25% averaged over the benchmarks considered in this work.

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Cited By

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  • (2021)Emergent design challenges for embedded systems and paths forwardProceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis10.1145/3478684.3479246(1-10)Online publication date: 30-Sep-2021

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Information

Published In

cover image ACM Conferences
NOCS '18: Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip
October 2018
182 pages
ISBN:9781538648933

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  • IEEE-CAS: Circuits & Systems

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IEEE Press

Publication History

Published: 04 October 2018

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Author Tags

  1. 3D NoC
  2. EDP
  3. TSV
  4. electromigration
  5. energy
  6. hardware attack
  7. latency
  8. security

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NOCS '18

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Overall Acceptance Rate 14 of 44 submissions, 32%

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View all
  • (2021)Emergent design challenges for embedded systems and paths forwardProceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis10.1145/3478684.3479246(1-10)Online publication date: 30-Sep-2021

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