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MAGIC: Malicious Aging in Circuits/Cores

Published: 02 April 2015 Publication History

Abstract

The performance of an IC degrades over its lifetime, ultimately resulting in IC failure. In this article, we present a hardware attack (called MAGIC) to maliciously accelerate NBTI aging effects in cores. In this attack, we identify the input patterns that maliciously age the pipestages of a core. We then craft a program that generates these patterns at the inputs of the targeted pipestage. We demonstrate the MAGIC-based attack on the OpenSPARC processor. Executing this program dramatically accelerates the aging process and degrades the processor’s performance by 10.92% in 1 month, bypassing existing aging mitigation and timing-error correction schemes. We also present two low-cost techniques to thwart the proposed attack.

References

[1]
Jaume Abella, Xavier Vera, and Antonio Gonzalez. 2007. Penelope: The NBTI-aware processor. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture. 85--96.
[2]
Hamed Abrishami, Safar Hatami, Behnam Amelifard, and Massoud Pedram. 2008. NBTI-aware flip-flop characterization and design. In Proceedings of the ACM Great Lakes symposium on VLSI (GLSVLSI’08). 29--34.
[3]
Mridul Agarwal, Bipul C. Paul, Ming Zhang, and Subhasish Mitra. 2007. Circuit failure prediction and its application to transistor aging. In Proceedings of the IEEE VLSI Test Symposium. 277--286.
[4]
Muhammad Ashraful Alam, Haldun Kufluoglu, Dhanoop Varghese, and Souvik Mahapatra. 2007. A comprehensive model for PMOS NBTI degradation: Recent progress. Microelectronics Reliability 47, 6 (2007), 853--862.
[5]
Todd Austin. 1999. DIVA: A reliable substrate for deep submicron microarchitecture design. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture. 196--207.
[6]
Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, and Sarma Vrudhula. 2006. Predictive modeling of the NBTI effect for reliable design. In Proceedings of the IEEE Custom Integrated Circuits Conference. 189--192.
[7]
David Bild, Gregory Bok, and Robert Dick. 2009. Minimization of NBTI performance degradation using internal node control. In Proceedings of IEEE Design Automation and Test in Europe. 148--153.
[8]
David R. Bild, Robert P. Dick, and Gregory E. Bok. 2012. Static NBTI reduction using internal node control. ACM IEEE Transactions on Design Automation Electronic Systems 17, 4 (2012), 45.
[9]
Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. 2011. The gem5 simulator. SIGARCH Computer Architecture News 39, 2 (2011), 1--7.
[10]
Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, and Vivek K. De. 2011. A 45 nm resilient microprocessor core for dynamic variation tolerance. Journal of Solid-State Circuits 46, 1 (2011), 194--208.
[11]
Soonyoung Cha, Chang-Chih Chen, Taizhi Liu, and Linda S. Milor. 2014. Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements. In Proceedings of VLSI Test Symposium (VTS’14). 1--6.
[12]
Ashutosh Chakraborty and David Z. Pan. 2011. Controlling NBTI degradation during static burn-in testing. In Proceedings of the Asia and South Pacific Design Automation Conference. 597--602.
[13]
Srini Chakravarthi, Anand Krishnan, Vijay Reddy, Chuck Machala, and Srikanth Krishnan. 2004. A comprehensive framework for predictive modeling of negative bias temperature instability. In Proceedings of the Reliability Physics Symposium. 273--282.
[14]
Simone Corbetta and William Fornaciari. 2012. NBTI mitigation in microprocessor designs. In Proceedings of ACM Great Lakes Symposium on VLSI. 33--38. Retrieved from http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2012.html#CorbettaF12.
[15]
Cyanogen. Cyanogenmod Forum. Retrieved from http://forum.cyanogenmod.com/.
[16]
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, and Trevor Mudge. 2003. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture. 7--18.
[17]
Kai Feng, Thomas Fleischman, Ping-Chuan Wang, Xiaojin Wei, and Zhijian Yang. May 5, 2011. On-chip accelerated failure indicator. U.S. Patent 3247503. (May 5, 2011).
[18]
Tibor Grasser, Hans Reisinger, Paul-Jürgen Wagner, Franz Schanovsky, Wolfgang Gös, and Ben Kaczer. 2010. The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability. In Proceedings of the International Reliability Physics Symposium (IRPS’10). 16--25.
[19]
Benson Inkley. 2008. Digital thermal sensors and the DTS based thermal specification for the Intel Core i7 Processor. Intel Developer Forum (IDF). Retrieved from http://lenry.atw.hu/tjmax.pdf.
[20]
Mangesh Kasbekar and Chita R. Das. 2001. Selective checkpointing and rollbacks in multithreaded distributed systems. In Proceedings of the International Conference on Distributed Computing Systems. 39--46.
[21]
Seyab Khan, Nor Zaidi Haron, Said Hamdioui, and Francky Catthoor. 2011. NBTI monitoring and design for reliability in nanoscale circuits. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. 68--76.
[22]
Haldun Kufluoglu and Muhammad Ashraful Alam. 2007. A generalized reaction-diffusion model with explicit H-H2 dynamics for Negative-Bias Temperature-Instability (NBTI) degradation. IEEE Transactions on Electron Devices 54, 5 (2007), 1101--1107.
[23]
Halil Kükner, Moustafa Khatib, Sebastien Morrison, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van Der Perre, Rudy Lauwereins, and Guido Groeseneken. 2014. Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology. In Proceedings of the International Symposium on Quality Electronic Design (ISQED’14). 473--479.
[24]
Yongho Lee and Taewhan Kim. 2011. A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. In Proceedings of the Asia and South Pacific Design Automation Conference. 603--608.
[25]
Bao Liu and Chiung-Hung Chen. 2014. Testing, diagnosis and repair methods for NBTI-induced SRAM faults. In Proceedings of the International Conference on IC Design and Technology. 1--4.
[26]
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, and Xuan Zeng. 2009. Statistical reliability analysis under process variation and aging effects. In Proceedings of the IEEE/ACM Design Automation Conference. 514--519.
[27]
Souvik Mahapatra, Dipankar Saha, Dhanoop Varghese, and Bharat. Kumar. 2006. On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress. IEEE Transactions on Electron Devices 53, 7 (2006), 1583--1592.
[28]
Christopher Mims. 2013. If It Aint Broke, Of Course Apple Is Engaging in Planned Obsolescence. Retrieved from http://qz.com/141297/of-courseapple-is-engaging-in-planned-obsolescence.
[29]
Predictive Technology Model. 2007. Introduction. Retrieved from http://ptm.asu.edu/.
[30]
Fabian Oboril, Farshad Firouzi, Saman Kiamehr, and Mehdi Baradaran Tahoori. 2012. Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions. In Proceedings of Hardware/Software Codesign and System Synthesis. 443--452. Retrieved from http://dblp.uni-trier.de/db/conf/codes/codes2012.html#OborilFKT12.
[31]
Oracle. 2006a. OpenSPARC T1. Retrieved from http://www.oracle.com/technetwork/systems/opensparc/opensparc-t1-page-1444609.html.
[32]
Oracle. 2006b. OpenSPARC T1 Microarchitecture Specification.
[33]
Catherine Rampell. 2013. Cracking the Apple Trap. Retrieved from http://www.nytimes.com/2013/11/03/magazine/why-apple-wants-to-bust-your-iphone.html.
[34]
Vikram G. Rao and Hamid Mahmoodi. 2011. Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology. In Proceedings of IEEE International Conference on Computer Design. 439--440.
[35]
Rosana Rodriguez, James Stathis, and Barry Linder. 2003. Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters. In Proceedings of IEEE International Reliability Physics Symposium. 11--16.
[36]
Matt Rosoff. 2012. Microsoft: Apple Makes Old iPhones ‘Unusably Slow’ on Purpose. Retrieved from http://www.businessinsider.com/microsoft-apple-makes-old-iphones-unusably-slow-on-purpose-2012-3.
[37]
Eric Rotenberg. 1999. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In Proceedings of the International Symposium on Fault-Tolerant Computing. 84--91.
[38]
Subhendu Roy and David Z. Pan. 2014. Reliability aware gate sizing combating NBTI and oxide breakdown. In Proceedings of the International Conference on VLSI Design and Embedded Systems. 38--43.
[39]
Dipankar Saha, Dhanoop Varghese, and Souvik Mahapatra. 2006. Role of anode hole injection and valence band hole tunneling on interface trap generation during hot carrier injection stress. IEEE Electron Device Letters 27, 7 (2006), 585--587.
[40]
Smruti Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari, and Josep Torrellas. 2008. VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions on Semiconductor Manufacturing 21, 1 (2008), 3--13.
[41]
Vinay Saripalli, Guangyu Sun, Asit Mishra, Yuan Xie, Suman Datta, and Vijaykrishnan Narayanan. 2011. Exploiting heterogeneity for energy efficiency in chip multiprocessors. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1, 2 (2011), 109--119.
[42]
Dieter K. Schroder. 2007. Negative bias temperature instability: What do we understand? Microelectron Reliability 47, 6 (2007), 841--852.
[43]
Ozgur Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, Ramesh Karri, Yier Jin, Ke Huang, and Yiorgos Makris. 2013. Reconciling the IC test and security dichotomy. In Proceedings of European Test Symposium (ETS’13). 1--6.
[44]
Hunter Skipworth. 2012. The Myth of the Sony Kill Switch. Retrieved from http://www.telegraph.co.uk/technology/news/7054587/Themyth-of-the-Sony-kill-switch.html.
[45]
Ketul B. Sutaria, Jyothi B. Velamala, Athul Ramkumar, and Yu Cao. 2015. Compact modeling of BTI for circuit reliability analysis. In Circuit Design for Reliability. Springer, 93--119.
[46]
Abhishek Tiwari and Josep Torrellas. 2008. Facelift: Hiding and slowing down aging in multicores. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture. 129--140.
[47]
Randy Torrance and Dick James. 2011. The state-of-the-art in semiconductor reverse engineering. In Proceedings of the IEEE/ACM Design Automation Conference. 333--338.
[48]
Rakesh Vattikonda, Wenping Wang, and Yu Cao. 2006. Modeling and minimization of PMOS NBTI effect for robust nanometer design. In Proceedings of the IEEE/ACM Design Automation Conference. 1047--1052.
[49]
Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma Vrudhula, Frank Liu, and Yu Cao. 2010. The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis. IEEE Transactions on Very Large Scale Integration Systems 18, 2 (2010), 173--183.
[50]
Yao Wang, Sorin D. Cotofana, and Liang Fang. 2012. Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. In Proceedings of the International Symposium on Nanoscale Architectures (NANOARCH’12). 109--115.
[51]
Sheng Wei and Miodrag Potkonjak. 2011. Integrated circuit security techniques using variable supply voltage. In Proceedings of IEEE/ACM Design Automation Conference. 248--253.
[52]
Gil Wolrich, Edward McLellan, Larry Harada, James Montanaro, and Robert Yodlowski. 1984. A high performance floating point coprocessor. IEEE Journal of Solid-State Circuits 19, 5 (1984), 690--696.
[53]
Tim Worstall. 2013. Certainly theres planned obsolescence in Apples iKit its just not planned by Apple. Retrieved from http://www.forbes.com/sites/timworstall/2013/10/31/certainly-theres-planned-obsolescence-in-apples-ikit-its-just-not-planned-by-apple.
[54]
Teong-San Yeoh and Shze-Jer Hu. 1998. Influence of MOS transistor gate oxide breakdown on circuit performance. In Proceedings of IEEE International Conference on Semiconductor Electronics. 59--63.

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Published In

cover image ACM Transactions on Architecture and Code Optimization
ACM Transactions on Architecture and Code Optimization  Volume 12, Issue 1
April 2015
201 pages
ISSN:1544-3566
EISSN:1544-3973
DOI:10.1145/2744295
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 02 April 2015
Accepted: 01 January 2015
Revised: 01 January 2015
Received: 01 June 2014
Published in TACO Volume 12, Issue 1

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Author Tags

  1. Hardware security
  2. NBTI aging
  3. malicious aging acceleration

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  • Research-article
  • Research
  • Refereed

Funding Sources

  • Center for Interdisciplinary Studies in Security and Privacy (CRISSP) New York, CRISSP-AD
  • National Science Foundation Computing and Communication Foundation (NSFCCF)

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  • (2024)UnTrustZone: Systematic Accelerated Aging to Expose On-chip Secrets2024 IEEE Symposium on Security and Privacy (SP)10.1109/SP54263.2024.00069(4107-4124)Online publication date: 19-May-2024
  • (2024)Investigating the Influence of Process Variability on Asymmetric Multicore Processors2024 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI62366.2024.10703977(1-5)Online publication date: 2-Sep-2024
  • (2023)Aging-Induced Failure Prognosis via Digital SensorsProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590204(703-708)Online publication date: 5-Jun-2023
  • (2022)Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation PredictionJournal of Circuits, Systems and Computers10.1142/S021812662350175X32:10Online publication date: 31-Dec-2022
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  • (2021)Emergent design challenges for embedded systems and paths forwardProceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis10.1145/3478684.3479246(1-10)Online publication date: 30-Sep-2021
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