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Revisiting wear leveling design on compression applied 3D NAND flash memory: work-in-progress

Published: 30 September 2018 Publication History

Abstract

Compression has been demonstrated as an efficient method for lifetime improvement on flash memory. However, data compression ratios are various, which bring proportional wearing on flash pages. Furthermore, the compression schemes have still not been considered in the design of the state-of-the-art wear leveling schemes. Thus, there will be some waste on lifetime exploitation, especially for three-dimensional (3D) NAND flash memory. 3D NAND flash memory is developed to boost the storage capacity by stacking memory cells vertically. However, in 3D NAND flash, one critical characteristic is that its endurance is significantly varied from blocks to pages. Thus, it is necessary to revisit the wear leveling mechanism for compression applied 3D NAND flash memory for further lifetime improvement.

References

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Micheloni, Rino and Crippa, Luca and Marelli, Alessia, "Inside NAND Flash Memories" Springer, 2010.
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Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao, Yong Guan, "MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems," in DAC, 2011.
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Lee, Sungjin and Park, Jihoon and Fleming, Kermin and Kim, Jihong and et al., "Improving performance and lifetime of solid-state drives using hardware-accelerated compression," IEEE TCE, 2011, pp. 1732--1739.
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Zuck, Aviad and Toledo, Sivan and Sotnikov, Dmitry and Harnik, Danny, "Compression and SSDs: Where and how?," in INFLOW, 2014.
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Micheloni, R.,"3D Flash Memories," 2016.
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K. T. Park and D. S. Byeon and D. H. Kim,"A world's first product of three-dimensional vertical NAND Flash memory and beyond," in NVMTS, 2014.
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Ming-Chang Yang and Yuan-Hao Chang and Che-Wei Tsao and Po-Chun Huang,"New ERA: New efficient reliability-aware wear leveling for endurance enhancement of flash storage devices," in DAC, 2013.
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Yangyang Pan and Guiqiang Dong and Tong Zhang,"Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes," in TVLSI, 2013.
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Vic Ye,"The Solution to the Bit Error Non-uniformity of 3D NAND," in EMS, 2017.

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Published In

cover image ACM Conferences
CODES '18: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis
September 2018
64 pages
ISBN:9781538655627

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  • IEEE CAS

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IEEE Press

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Published: 30 September 2018

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  1. 3D flash memory
  2. compression
  3. wear leveling

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  • Research-article

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ESWEEK '18
ESWEEK '18: Fourteenth Embedded Systems Week
September 30 - October 5, 2018
Turin, Italy

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Overall Acceptance Rate 280 of 864 submissions, 32%

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