Nothing Special   »   [go: up one dir, main page]

skip to main content
10.5555/290940.290951acmconferencesArticle/Chapter ViewAbstractPublication PagesmicroConference Proceedingsconference-collections
Article
Free access

Simple vector microprocessors for multimedia applications

Published: 01 November 1998 Publication History
First page of PDF

References

[1]
Krste Asanovi~. Vector Microprocessors. PhD thesis, University of California at Berkeley, May 1998.
[2]
Krste Asanovit, James Beck, Bertrand Irissou, Brian Kingsbury, Nelson Morgan, and John Wawrzynek. The TO Vector Microprocessor. In Proceedings of Hot Chips VII, pages 187-196, Stanford, CA, August 1995.
[3]
William J. Bowhill et al. A 300MHz 64b Quad-Issue CMOS RISC Microprocessor. In Digest of Technical Papers for the International Solid-State Circuits Conference, pages 182-183,362, San Fransisco, CA, February 1995.
[4]
Doug Burger and James R, Goodman (Guest Editors). Billion-Transistor Architectures. IEEE Computer, 30(9):46--48, September 1997. Special issue on The Future of Microprocessors.
[5]
Digital Equipment Corperation. Advanced Technology for Visual Computing: Alpha Architecture with MVI. http://www, digital, com/semiconductorAnvibackgrounder, htm, March 1997.
[6]
Derek J. DeVries. A Vectorizing SUIF Compiler: Implementation and Performance. Master's thesis, University of Toronto, June 1997.
[7]
Keith Diefendorff and Pradeep K. Dubey. How Multimedia Workloads Will Change Processor Design. IEEE Computer, 30(9):43--45, September 1997.
[8]
P.J. Hemming and J.J. Wallace. How Not to Lie with Statistics: The Correct Way to Summarize Benchmark Results. Communications of the ACM, 29(3):218-221, March 1986.
[9]
Bruce A. Gieseke et al. A 600MHz Superscalar RISC Microprocessor with Out-Of-Order Execution. In Digest of Technical Papers for the International Solid-State Circuits Conference, pages 176-177,451, San Fransisco, CA, February 1997.
[10]
Silicon Graphics. MIPS R10000 Microprocessor. http ://www. s g i. c om/-MIP S/p roducts/r 1 Ok/T5 _Die. html, 1996.
[11]
Silicon Graphics. MIPS RISC R5000 Microprocessor. http ://www. s g i. com/MIPS/p roducts/r5000, 1996.
[12]
Silicon Graphics. MIPS Extension for Digital Media with 3D. http://www, sgi. com/MIPS/arch/ISA5/- index, html#MIPSV_indx, March 1997.
[13]
Paul E. Gronowski et al. A 433MHz 64b Quad-Issue RISC Microprocessor, in Digest of Technical Papers for the International Solid-State Circuits Conference, pages 222-223,449, San Fransisco, CA, February 1996.
[14]
Linley Gwennap. Class of '94 Has Mixed Success. Microprocessor Report, 11 (14), Oct 27 1997.
[15]
Linley Gwennap. Is it Soup Yet? MicroprocessorReport, 11(2), Feb 19 1997.
[16]
Linley Gwennap. RISC Disappointments Mount. Microprocessor Report, 11 (17), Dec 29 1997.
[17]
John L. Hennessy and David A. Patterson. Computer Architecture: A Quantitative Approach, Second Edition. Morgan Kaufmann Publishers, San Fransisco, CA, 1996.
[18]
Intel. Software Benefits of Katmai New Instructions. http ://dev e lop e r. inte l. c onff drg/news/gcatma i. htm, 1998.
[19]
L. Kohn, G. Maturana, M. Tremblay, A. Prabhu, and G. Zyner. The Visual Instruction Set (VIS) in Ultra- SPARC. In Proceedings of the Compcon-95, pages 462- 469, March 1995.
[20]
Christoforos E. Kozyrakis and David A. Patterson. A New Direction for Computer Architecture Research. To be published in IEEE Computer., May 1998.
[21]
Ashok Kumar. The HP PA-8000 RISC CPU. IEEE Micro, 17(2):27-32, March-April 1997.
[22]
Corinna G. Lee. MIPS Vector Architecture Manual. In preparation., June 1997.
[23]
Corinna G. Lee and Derek J. DeVries. initial Results on the Performance and Cost of Vector Microprocessors. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 171-182, December 1997.
[24]
Ruby B. Lee. Accelerating Multimedia with Enhanced Microprocessors. IEEE Micro, 15(2):22-32, April 1995.
[25]
Ruby B. Lee. Subword Parallelism with MAX-2. IEEE Micro, 16(4):52-59, August 1996.
[26]
Jon Lotz et al. A Quad-Issue Out-of-Order RISC CPU. In Digest of Technical Papers for the International Solid- State Circuits Conference, pages 210-211,446, San Fransisco, CA, February 1996.
[27]
Motorola. Motorola AltiVec Technology: Home Page. http ://www. mot. con~SPS/PowerPC/AltiVec/, 1998.
[28]
Alex Peleg and Uri Wieser. MMX Technology Extensions to the Intel Architecture. IEEE Micro, 16(4): 10-20, August 1996.
[29]
John Wawrzynek, Krste Asanovit, Brian Kingsbury, James Beck, David Johnson, and Nelson Morgan. SPERT-II: A Vector Microprocessor System. IEEE Computer, 29(3):79-86, March 1996.
[30]
Kenneth C. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, 16(2):28--40, April 1996.

Cited By

View all

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
MICRO 31: Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
November 1998
321 pages
ISBN:1581130163

Sponsors

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 November 1998

Check for updates

Qualifiers

  • Article

Conference

MICRO98
Sponsor:

Acceptance Rates

MICRO 31 Paper Acceptance Rate 28 of 108 submissions, 26%;
Overall Acceptance Rate 484 of 2,242 submissions, 22%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)50
  • Downloads (Last 6 weeks)8
Reflects downloads up to 20 Nov 2024

Other Metrics

Citations

Cited By

View all
  • (2013)Parallel execution of Java loops on Graphics Processing UnitsScience of Computer Programming10.1016/j.scico.2011.06.00478:5(458-480)Online publication date: 1-May-2013
  • (2013)Design, implementation, and evaluation of a low-complexity vector-core for executing scalar/vector instructionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2013.02.00373:6(836-850)Online publication date: 1-Jun-2013
  • (2012)A compiler framework for extracting superword level parallelismACM SIGPLAN Notices10.1145/2345156.225410647:6(347-358)Online publication date: 11-Jun-2012
  • (2012)A compiler framework for extracting superword level parallelismProceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/2254064.2254106(347-358)Online publication date: 11-Jun-2012
  • (2009)Automatic parallelization for graphics processing unitsProceedings of the 7th International Conference on Principles and Practice of Programming in Java10.1145/1596655.1596670(91-100)Online publication date: 27-Aug-2009
  • (2007)An embedded coherent-multithreading multimedia processor and its programming modelProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278646(652-657)Online publication date: 4-Jun-2007
  • (2007)ALPACM Transactions on Architecture and Code Optimization10.1145/1216544.12165464:1(3-es)Online publication date: 1-Mar-2007
  • (2006)A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architecturesProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131581(363-368)Online publication date: 6-Mar-2006
  • (2006)Implementing virtual memory in a vector processor with software restart markersProceedings of the 20th annual international conference on Supercomputing10.1145/1183401.1183422(135-144)Online publication date: 28-Jun-2006
  • (2006)Multi-platform Auto-vectorizationProceedings of the International Symposium on Code Generation and Optimization10.1109/CGO.2006.25(281-294)Online publication date: 26-Mar-2006
  • Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media