Cited By
View all- Witharana HLyu YCharles SMishra P(2022)A Survey on Assertion-based Hardware VerificationACM Computing Surveys10.1145/351057854:11s(1-33)Online publication date: 9-Sep-2022
On-Chip Verification of NoCs Using Assertion Processors
Authors: 
Mohammad Reza Kakoee, 
M. H. Neishaburi, 
Masoud Daneshtalab, Saeed Safari, Zainalabedin NavabiAuthors Info & Claims
Pages 535 - 538
Abstract
NoC verification has become an increasingly difficult task due to the growing complexity of these systems. In this paper, we propose a methodology based on assertions for on-chip verification of NoCs. We have a Local Assertion Processor (LAP) in each core to manage the outputs of assertions inside it. To route assertions' outputs toward this processor, we offer a boundary scan chain mechanism. Moreover, after detecting error, each LAP dispatches a packet called error packet to a Global Assertion Processor (GAP) which receives error packets from all cores and performs necessary actions regarding to errors and their severities. Finally, in order to evaluate our method, we apply it on an NoC structure and show the experimental results.
Index Terms
- On-Chip Verification of NoCs Using Assertion Processors
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Published In
August 2007
674 pages
ISBN:076952978X
Publisher
IEEE Computer Society
United States
Publication History
Published: 29 August 2007
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Cited By
View all- Witharana HLyu YCharles SMishra P(2022)A Survey on Assertion-based Hardware VerificationACM Computing Surveys10.1145/351057854:11s(1-33)Online publication date: 9-Sep-2022