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BDDMAP: a technology mapper based on a new covering algorithm

Published: 01 July 1992 Publication History
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References

[1]
D. Gregory, K. Bartlett, A. de Geus, and G. Ha~htel, "Socrates: a system for automatically synthesizing and optimizing combinational logic," in Proceedings of the 23rd A CM/IEEE Design Automation Con.terence, pp. 79-85, ACM/IEEE, June 1986.
[2]
K. Keutzer, "Dagon: technology binding and local optimization by dag matching," in Proceedings of the ~4th A GM/IEEE Design Automation Con}erence, pp. 341- 347, ACM/IEEE, June 1987.
[3]
M. Lega, "Mapping properties of multi-level logic synthesis operations," in Proceedings o.f the ICCD'88, pp. 257-260, ACM/IEEE, 1988.
[4]
F. Mailhot and G. De Micheli, "Technology mapping using boolean matching and don't care sets," in Proceedings o} the EDA C'90, pp. 212-216, 1990.
[5]
W. Joyner, L. Trevillyan, D. Brand, T. Nix, and S. Gundersen, "Technology adaptation in logic synthesis," in Proceedings of the 23rd A CM/IEEE Design A utomation Conference, pp. 94-100, ACM/IEEE, June 1986.
[6]
S. Yang, "Logic synthesis and optimization benchmarks user guide," 1991. Version 3.1.
[7]
E. Detjens, G. Gannot, R. RudeU, A. Sangiovanni- Vincentelli, and A. Wang, "Technology mapping in mis," in Proceedings o} the ICCAD, pp. 116-119, ACM/IEEE, November 1987.

Cited By

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  • (1997)Addressing Early Design-For-Test Synthesis in a Production EnvironmentProceedings of the 1997 IEEE International Test Conference10.5555/844384.845728Online publication date: 1-Nov-1997
  • (1997)Design methodology for the S/390 parallel enterprise server G4 microprocessorsIBM Journal of Research and Development10.1147/rd.414.051541:4-5(515-547)Online publication date: 1-Jul-1997
  • (1997)A pseudo-hierarchical methodology for high performance microprocessor designProceedings of the 1997 international symposium on Physical design10.1145/267665.267702(124-129)Online publication date: 1-Apr-1997
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cover image ACM Conferences
DAC '92: Proceedings of the 29th ACM/IEEE Design Automation Conference
July 1992
752 pages
ISBN:089791516X

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 1992

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DAC92
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DAC92: The 29th ACM/IEEE-CS Design Automation Conference
June 8 - 12, 1992
California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (1997)Addressing Early Design-For-Test Synthesis in a Production EnvironmentProceedings of the 1997 IEEE International Test Conference10.5555/844384.845728Online publication date: 1-Nov-1997
  • (1997)Design methodology for the S/390 parallel enterprise server G4 microprocessorsIBM Journal of Research and Development10.1147/rd.414.051541:4-5(515-547)Online publication date: 1-Jul-1997
  • (1997)A pseudo-hierarchical methodology for high performance microprocessor designProceedings of the 1997 international symposium on Physical design10.1145/267665.267702(124-129)Online publication date: 1-Apr-1997
  • (1995)Logic verification methodology for PowerPC microprocessorsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217535(234-240)Online publication date: 1-Jan-1995
  • (1994)Boolean matching of sequential elementsProceedings of the 31st annual Design Automation Conference10.1145/196244.196617(691-697)Online publication date: 6-Jun-1994
  • (1993)Verification of large synthesized designsProceedings of the 1993 IEEE/ACM international conference on Computer-aided design10.5555/259794.259883(534-537)Online publication date: 7-Nov-1993

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