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Program phase detection and exploitation

Published: 25 April 2006 Publication History

Abstract

Studies of application behavior reveal the nested repetition of large and small program phases, with significant variation among phases in such characteristics as memory reference patterns, memory and energy usage, I/O activity, and occupancy of micro-architectural resources. In this project, we study theories and techniques for reliably predicting and exploiting phased behavior, so an advanced execution environment may allocate resources in a way that better matches program needs, or to transform programs so that their needs better match the available resources. In this paper, we present the basic components of the study and report the progress in the past half year.

References

[1]
C. Amza, A. Cox, S. Dwarkadas, and W. Zwaenepoel. Software DSM protocols that adapt between single writer and multiple writer. In Proc. of the 3rd Intl. Symp. on High Performance Computer Architecture, pages 261- 271, San Antonio, TX, February 1997.
[2]
C. Amza, A. L. Cox, S. Dwarkadas, L.-J. Jin, K. Rajamani, and W. Zwaenepoel. Adaptive protocols for software distributed shared memory. In Proc. of the IEEE, March 1999.
[3]
R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. In International Symposium on Microarchitecture, pages 245-257, Monterey, California, Dec. 2000.
[4]
R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. A Dynamically Tunable Memory Hierarchy. IEEE Transactions on Computers, 52(10):1243- 1258, Oct. 2003.
[5]
D. Chaver, L. Pinuel, M. Prieto, F. Tirado, and M. Huang. Branch Prediction on Demand: an Energy-Efficient Solution. In International Symposium on Low-Power Electronics and Design, Seoul, Korea, Aug. 2003.
[6]
D. Chen, C. Tang, X. Chen, S. Dwarkadas, and M. L. Scott. Multi-level shared state for distributed systems. In Proc. of the 2002 Intl. Conf. on Parallel Processing, pages 131-140, Vancouver, BC, Canada, August 2002.
[7]
F. Darema, G. F. Pfister, and K. So. Memory access patterns of parallel scientific programs. In Proceedings of the ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, May 1987.
[8]
S. Dropsho, A. Buyuktosunoglu, R. Balasubramonian, D. Albonesi, S. Dwarkadas, G. Semeraro, G. Magklis, and M. Scott. Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. In International Conference on Parallel Architectures and Compilation Techniques, pages 141-152, Charlottesville, Virginia, Sept. 2002.
[9]
E. Duesterwald, C. Cascaval, and S. Dwarkadas. Characterizing and Predicting Program Behavior and its Variability. In International Conference on Parallel Architectures and Compilation Techniques, pages 220-231, New Orleans, Louisiana, Sept. 2003.
[10]
A. El-Moursy, R. Garg, D. H. Albonesi, and S. Dwarkadas. Compatible phase co-scheduling on a cmp of multi-threaded processors. In Proceedings of 2006 International Parallel and Distribute Processing Symposium (IPDPS), April 2006.
[11]
M. Huang, D. Chaver, L. Pinuel, M. Prieto, and F. Tirado. Customizing the Branch Predictor to Reduce Complexity and Energy Consumption. IEEE Micro, 23(5):12-25, Sept. 2003.
[12]
M. Huang, J. Renau, and J. Torrellas. Positional Adaptation of Processors: Application to Energy Reduction. In International Symposium on Computer Architecture, pages 157-168, San Diego, California, June 2003.
[13]
R. Huang, A. Garg, and M. Huang. Software-Hardware Cooperative Memory Disambiguation. In International Symposium on High-Performance Computer Architecture, Austin, Texas, Feburary 2006.
[14]
S. Ioannidis, U. Rencuzogullari, R. Stets, and S. Dwarkadas. CRAUL: Compiler and run-time integration for adaptation under load. Journal of Scientific Programming, pages 261-273, August 1999.
[15]
W. Liu and M. Huang. EXPERT: Expedited Simulation Exploiting Program Behavior Repetition. In International Conference on Supercomputing, St. Malo, France, June-July 2004.
[16]
G. Magklis, M. Scott, G. Semeraro, D. Albonesi, and S. Dropsho. Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. In International Symposium on Computer Architecture, pages 14-25, San Diego, California, June 2003.
[17]
G. Magklis, G. Semeraro, D. H. Albonesi, S. Dropsho, S. Dwarkadas, and M. L. Scott. Dynamic frequency and voltage scaling for a multiple clock domain microprocessor. IEEE Micro, 23(6):62-68, November-December 2003.
[18]
A. E. Papathanasiou and M. L. Scott. Energy efficiency through burstiness. In Proc. of the 5th IEEE Workshop on Mobile Computing Systems and Applications, Monterey, CA, October 2003.
[19]
A. E. Papathanasiou and M. L. Scott. Energy efficient prefetching and caching. In Proc. of the USENIX 2004 Technical Conf., Boston, MA, June-July 2004.
[20]
U. Rencuzogullari and S. Dwarkadas. Dynamic adaptation to available resources for parallel computing in an autonomous network of workstations. In 8th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, June 2001.
[21]
U. Rencuzogullari and S. Dwarkadas. A technique for adaptation to available resources on clusters independent of synchronization methods used. In International Conference on Parallel Processing, Aug. 2002.
[22]
X. Shen, C. Ding, S. Dwarkadas, and M. L. Scott. Characterizing phases in service-oriented applications. Technical Report TR 848, Department of Computer Science, University of Rochester, November 2004.
[23]
X. Shen, Y. Zhong, and C. Ding. Locality Phase Prediction. In International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, Oct. 2004.
[24]
R. Stets, S. Dwarkadas, L. I. Kontothanassis, U. Rencuzogullari, and M. L. Scott. The effect of network total order, broadcast, and remote-write capability on networkbased shared memory computing. In Proc. of the 6th Intl. Symp. on High Performance Computer Architecture, Toulouse, France, January 2000.
[25]
C. Zhang, C. Ding, M. Ogihara, Y. Zhong, and Y. Wu. A hierarchical model of data locality. In Proceedings of ACM Symposium on Principles of Programming Languages, Charleston, SC, January 2006.

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  • (2008)Performance modeling of parallel applications for grid schedulingJournal of Parallel and Distributed Computing10.1016/j.jpdc.2008.02.00668:8(1135-1145)Online publication date: 1-Aug-2008

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Published In

cover image ACM Other conferences
IPDPS'06: Proceedings of the 20th international conference on Parallel and distributed processing
April 2006
399 pages
ISBN:1424400546

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  • IEEE CS TCPP: IEEE Computer Society Technical Committee on Parallel Processing

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IEEE Computer Society

United States

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Published: 25 April 2006

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  • (2008)Performance modeling of parallel applications for grid schedulingJournal of Parallel and Distributed Computing10.1016/j.jpdc.2008.02.00668:8(1135-1145)Online publication date: 1-Aug-2008

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