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A dynamic element matching circuit for multi-bit delta-sigma modulators

Published: 27 January 2004 Publication History

Abstract

A 30k-gate dynamic element matching circuit for bandpass modulators with a 4-bit quantizer is designed by using 0.35-μm CMOS technology. Second-order bandpass mismatch-shaping algorithm improves the signal-to-noise ratio by ~30dB (~5 bit). The core circuit area and the estimated operation speed were 1.44 mm2 and 20 MHz, respectively.

References

[1]
L. R. Carley, "A Noise-Shaping Coder Topology for Bit Converters," IEEE J. Solid-State Circuits, Vol. 24, pp. 267--273, 1989
[2]
I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S. -L. Chan, "A 90-dB SNR 2.5 MHz Output-Rate ADC Using Cascaded Multibit Delta-Sigma Modulation at 8x Oversampling Ratio," IEEE J. Solid-State Circuits, Vol. 35 pp. 1280--1828, 2000.
[3]
A. Yasuda, H. Tanimoto, and T. Iida, "A 100kHz, 9.6mW Multi-bit ΔΣ DAC and ADC using Noise Shaping Dynamic Element Matching with a Tree Structure" IEEE ISSCC Dig. of Tech. papers, Vol. 41, pp. 64--65, Feb. 1998.
[4]
T. Shui, R. Schreier, F. Hudson, "Mismatch Shaping for a Current-Mode Multibit Delta-Sigma DAC," IEEE J. Solid-State Circuits, Vol. 34, pp. 331--358, 1999.
  1. A dynamic element matching circuit for multi-bit delta-sigma modulators

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    cover image ACM Conferences
    ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference
    January 2004
    957 pages
    ISBN:0780381750

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    Published: 27 January 2004

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