Cited By
View all- Aboudina MRazavi B(2018)A new DAC mismatch shaping technique for sigma-delta modulatorsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2010.208317257:12(966-970)Online publication date: 12-Dec-2018
Multibit delta-sigma modulator with noise-shaping dynamic element matching
Pages 1125 - 1133
Abstract
This paper describes a fifth-order multibit low-pass delta-sigma modulator employing a proposed noise-shaping dynamic element matching (NS-DEM) technique to remove DAC nonlinearity error. Unlike most existing DEMs that trade SNR for SFDR, the proposed technique improves both SFDR and SNR. The noise shaping is incorporated in the first integrator of the loop filter without any additional analog circuitry. The fabricated modulator chip achieves 94-dB SFDR and 78-dB DR in 2.2-MHz BW and meets the ADSL2+ specifications.
References
[1]
L. R. Carley, A noise-shaping coder topology for 15+ bit converters, IEEE J. Solid-State Circuits, vol. 28, no. 2, pp. 267-273, Apr. 1989.
[2]
R. T. Baird and T. S. Fiez, Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 12, pp. 753-762, Dec. 1995.
[3]
Fujimori et al., "A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8 × oversampling ratio," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1820-1828, Dec. 2000.
[4]
K. Vleugels, S. Rabii, and B. A. Wooley, "A 2.5-V sigma-delta modulator for broadband communication applications," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1887-1899, Dec. 2001.
[5]
M. R. Miller and C. S. Petrie, "A multibit sigma-delta ADC for multimode receivers," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 475-482, Mar. 2003.
[6]
R. E. Radke, A. Eshraghi, and T. S. Fiez, "A 14-bit current-mode ΔΣ DAC based upon rotated data weighted averaging," IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1074-1084, Aug. 2000.
[7]
T. H. Kuo, K. D. Chen, and H. R. Yeng, "A wideband CMOS sigma delta modulator with incremental data weighted averaging," IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 11-17, Jan. 2002.
[8]
Y. I. Park et al., "A 16-bit, 5-MHz multi-bit sigma-delta ADC using adaptively randomized DWA," in Proc. IEEE Custom Integrated Circ. Conf., Sep. 2003, pp. 7-2.
[9]
M. Vadipour, "Techniques for preventing tonal behavior of data weighted averaging algorithm in ΔΣ modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 11, pp. 1137-1144, Nov. 2000.
[10]
A. A. Hamoui and K. W. Martin, "High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broadband applications," IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 51, no. 1, pp. 72-85, Jan. 2004.
[11]
I. Galton, "Spectral shaping of circuit errors in digital-to-Analog converters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 10, pp. 808-817, Oct. 1997.
[12]
H. T. Jensen and I. Galton, "A reduced-complexity mismatch-shaping DAC for delta-sigma data converters," in Proc. IEEE Int. Symp. Circuits Syst., Jun. 31, 1998, vol. 1, pp. 504-507.
[13]
J. Welz, I. Galton, and E. Fogleman, "Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 48, no. 11, pp. 1014-1027, Nov. 2001.
[14]
H.-Y. Hsieh and L. Lin, "A first-order tree-structured DAC with reduced signal-band noise," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 5, pp. 392-396, May 2007.
[15]
A. Fishov, E. Siragusa, J. Welz, E. Fogleman, and I. Galton, "Segmented mismatch-shaping D/A conversion," in Proc. IEEE ISCAS, May 2002, vol. 4, pp. 679-682.
[16]
Z. Zhang and G. C. Temes, "A segmented data-weighted- averaging technique," in Proc. Int. Symp. Circuits Syst., May 2007, pp. 481-484.
[17]
O. J. A. P. Nys and R. K. Henderson, "An analysis of dynamic element matching techniques in sigma-delta modulation," in Proc. Int. Symp. Circuits Syst., May 12-15, 1996, vol. 1, pp. :231-234.
[18]
G. Yves, Michiel Steyaert and Willy Sansen, Design of Multi-Bit Delta-Sigma A/D Converters. Boston, MA: Kluwer, c2002.
[19]
H. A. C. T. Mervyn, "A novel architecture for reducing the sensitivity of multibit sigma-delta ADCs to DAC nonlinearity," in Proc. Int. Symp. Circuits Syst., May 1995, vol. 1, pp. 17-20.
[20]
J. Chen and Y. P. Xu, "A novel noise shaping DAC for multi-bit sigma-delta modulator," IEEE Trans Circuits Syst. II, Exp. Briefs, vol. 53, no. 5, pp. 344-348, May 2006.
[21]
R. Schreier, "Delta sigma toolbox: An Open Exchange for the MATLAB and Simulink User Community," Dec. 2004.
[22]
R. Jiang and T. S. Fiez, "A 14-bit ΔΣ ADC with 8 × OSR and 4-MHz conversion bandwidth in a 0.18-µm CMOS process," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 63-74, Jan. 2004.
[23]
R. Behzad, "Switched-Capacitor amplifier," in Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001, pp. 435-436.
[24]
R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, "Design-oriented estimation of thermal noise in switched-capacitor circuits," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 52, no. 11, pp. 2358-2368, Nov. 2005.
[25]
B. Thomas, Optimal Design of Operational Transconductance Amplifiers with Application for Low Power DS Modulators. Konstanz, Germany: Hartung-Gorre Verlag, 2002.
[26]
B. Pio, Broadband Sigma-Delta A/D Converters. Konstanz, Germany: Hartung-Gorre Verlag, 2004.
Recommendations
Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs
Special issue on ISCAS2008This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (ΔΣ) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed ...
A 0.13µm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications
This paper describes the design and experimental characterization of a 0.13@mm CMOS switched-capacitor reconfigurable cascade @S@D modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level ...
Experimental implementation of $$\Delta \Sigma $$ΔΣAD modulator with dynamic analog components
This paper presents an experimental prototype of 2nd-order multi-bit $$\Delta \Sigma $$ΔΣAD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
Publisher
IEEE Press
Publication History
Published: 01 June 2009
Received: 30 June 2008
Author Tags
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 10 Nov 2024
Other Metrics
Citations
Cited By
View all- Aboudina MRazavi B(2018)A new DAC mismatch shaping technique for sigma-delta modulatorsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2010.208317257:12(966-970)Online publication date: 12-Dec-2018
View Options
View options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in