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- ArticleNovember 2024
BKDSNN: Enhancing the Performance of Learning-Based Spiking Neural Networks Training with Blurred Knowledge Distillation
AbstractSpiking neural networks (SNNs), which mimic biological neural systems to convey information via discrete spikes, are well-known as brain-inspired models with excellent computing efficiency. By utilizing the surrogate gradient estimation for ...
- ArticleAugust 2024
- research-articleJune 2023
VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations
- Chen Nie,
- Chenyu Tang,
- Jie Lin,
- Huan Hu,
- Chenyang Lv,
- Ting Cao,
- Weifeng Zhang,
- Li Jiang,
- Xiaoyao Liang,
- Weikang Qian,
- Yanan Sun,
- Zhezhi He
IEEE Transactions on Computers (ITCO), Volume 73, Issue 10Pages 2378–2390https://doi.org/10.1109/TC.2023.3285095Processing-in-Memory (PIM) has been widely explored for accelerating data-intensive machine learning computation that mainly consists of general-matrix-multiplication (GEMM), by mitigating the burden of data movements and exploiting the ultra-high memory ...
- short-paperJune 2023
XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph
GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023Pages 183–187https://doi.org/10.1145/3583781.3590288Recent advances in processing-in-cache (PIC) have enabled generalpurpose, high-performance computation with bit-serial computing techniques. Its outstanding performance relies on efficient hardware design, and also the software stack (i.e., Logic ...
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- research-articleAugust 2022
EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation ConferencePages 259–264https://doi.org/10.1145/3489517.3530660Model compression has been extensively investigated for supporting efficient neural network inference on edge-computing platforms due to the huge model size and computation amount. Recent researches embrace joint-way compression across multiple ...
- research-articleAugust 2022
SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation ConferencePages 1105–1110https://doi.org/10.1145/3489517.3530592Event-driven spiking neural networks (SNNs) have shown great promise for being strikingly energy-efficient. SNN neurons integrate the spikes, accumulate the membrane potential, and fire output spike when the potential exceeds a threshold. Existing SNN ...
- research-articleAugust 2022
PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration
- Fangxin Liu,
- Wenbo Zhao,
- Yongbiao Chen,
- Zongwu Wang,
- Zhezhi He,
- Rui Yang,
- Qidong Tang,
- Tao Yang,
- Cheng Zhuo,
- Li Jiang
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation ConferencePages 1087–1092https://doi.org/10.1145/3489517.3530575Deep hashing has gained growing momentum in large-scale image retrieval. However, deep hashing is computation- and memory-intensive, which demands hardware acceleration. The unique process of hash sequence computation in deep hashing is non-trivial to ...
- research-articleMay 2022
Self-terminating write of multi-level cell ReRAM for efficient neuromorphic computing
- Zongwu Wang,
- Zhezhi He,
- Rui Yang,
- Shiquan Fan,
- Jie Lin,
- Fangxin Liu,
- Yueyang Jia,
- Chenxi Yuan,
- Qidong Tang,
- Li Jiang
DATE '22: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in EuropePages 1251–1256The Resistive Random-Access-Memory (ReRAM) in crossbar structure has shown great potential in accelerating the vector-matrix multiplication, owing to the fascinating computing complexity reduction (from O(n2) to O(1)). Nevertheless, the ReRAM cells ...
- research-articleMay 2022
DTQAtten: leveraging <u>d</u>ynamic <u>t</u>oken-based quantization for efficient <u>atten</u>tion architecture
DATE '22: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in EuropePages 700–705Models based on the attention mechanism, i.e. transformers, have shown extraordinary performance in Natural Language Processing (NLP) tasks. However, their memory footprint, inference latency, and power consumption are still prohibitive for efficient ...
- research-articleFebruary 2022
N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores
FPGA '22: Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPages 112–122https://doi.org/10.1145/3490422.3502367Accelerating the neural network inference by FPGA has emerged as a popular option, since the reconfigurability and high performance computing capability of FPGA intrinsically satisfies the computation demand of the fast-evolving neural algorithms. ...
- research-articleJanuary 2022
HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine
ASPDAC '22: Proceedings of the 27th Asia and South Pacific Design Automation ConferencePages 226–231https://doi.org/10.1109/ASP-DAC52403.2022.9712542Binary Neural Networks (BNNs) have attracted tremendous attention in ReRAM-based Process-In-Memory (PIM) systems, since they significantly simplify the hardware-expensive peripheral circuits and memory footprint. Meanwhile, BNNs are proven to have ...
- research-articleDecember 2021
PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
2021 58th ACM/IEEE Design Automation Conference (DAC)Pages 583–588https://doi.org/10.1109/DAC18074.2021.9586231Graph Convolutional Network (GCN) is a promising but computing- and memory-intensive learning model. Processing-in-memory (PIM) architecture based on the ReRAM crossbar is a natural fit for GCN inference. It can reduce the data movements and compute the ...
- research-articleNovember 2021
Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)Pages 1–9https://doi.org/10.1109/ICCAD51958.2021.9643569Resistive Random-Access-Memory (ReRAM) crossbar is one of the most promising neural network accelerators, thanks to its in-memory and in-situ analog computing abilities for Matrix Multiplication-and-Accumulations (MACs). Nevertheless, the number of rows ...
- short-paperOctober 2021
AdaptiveGCN: Efficient GCN Through Adaptively Sparsifying Graphs
CIKM '21: Proceedings of the 30th ACM International Conference on Information & Knowledge ManagementPages 3206–3210https://doi.org/10.1145/3459637.3482049Graph Convolutional Networks (GCNs) have become the prevailing approach to efficiently learn representations from graph-structured data. Current GCN models adopt a neighborhood aggregation mechanism based on two primary operations, aggregation and ...
- research-articleSeptember 2021
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 14, Issue 4Article No.: 18, Pages 1–28https://doi.org/10.1145/3467476Field-programmable Gate Array (FPGA) is a high-performance computing platform for Convolution Neural Networks (CNNs) inference. Winograd algorithm, weight pruning, and quantization are widely adopted to reduce the storage and arithmetic overhead of CNNs ...
- research-articleSeptember 2021
Elf: accelerate high-resolution mobile deep vision with content-aware parallel offloading
- Wuyang Zhang,
- Zhezhi He,
- Luyang Liu,
- Zhenhua Jia,
- Yunxin Liu,
- Marco Gruteser,
- Dipankar Raychaudhuri,
- Yanyong Zhang
MobiCom '21: Proceedings of the 27th Annual International Conference on Mobile Computing and NetworkingPages 201–214https://doi.org/10.1145/3447993.3448628As mobile devices continuously generate streams of images and videos, a new class of mobile deep vision applications are rapidly emerging, which usually involve running deep neural networks on these multimedia data in real-time. To support such ...
- research-articleJune 2021
Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support
GLSVLSI '21: Proceedings of the 2021 Great Lakes Symposium on VLSIPages 347–352https://doi.org/10.1145/3453688.3461528This work presents HRAM, a SRAM-based hybrid memory bit-cell for energy-efficient in-memory computing purpose. The HRAM bit-cell consists of conventional 6T-SRAM for static data storage, and extra one accessing transistor and capacitor for caching data ...
- research-articleJune 2021
Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication
GLSVLSI '21: Proceedings of the 2021 Great Lakes Symposium on VLSIPages 15–20https://doi.org/10.1145/3453688.3461494ReRAM-based deep neural network (DNN) accelerator shows enormous potential because of ReRAM's high computational-density and power-efficiency. A typical feature of DNNs is that weight matrix size varies across diverse DNNs and DNN layers. However, ...