Open AccessProceeding Paper

Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers^†

Sakhybay Tynymbayev

¹,

Assel Mukasheva

^2,*

Kuanyshbek Ibragimov

³,

Adil Mukhamedgali

²,

Gani Sergazin

⁴

and

Teodor Iliev

⁵

International University of Information Technology, Almaty 050013, Kazakhstan

School of Information Technology and Engineering, Kazakh-British Technical University, Almaty 050000, Kazakhstan

Kazakh National University named after Al-Farabi, Almaty 050040, Kazakhstan

⁴

Academy of Logistics and Transport, Almaty 050012, Kazakhstan

⁵

Department of Telecommunications, University of Ruse, 7004 Ruse, Bulgaria

Author to whom correspondence should be addressed.

^†

Presented at the International Conference on Electronics, Engineering Physics and Earth Science (EEPES’24), Kavala, Greece, 19–21 June 2024.

Eng. Proc. 2024, 70(1), 6; https://doi.org/10.3390/engproc2024070006

Published: 24 July 2024

(This article belongs to the Proceedings of International Conference on Electronics, Engineering Physics and Earth Science (EEPES 2024))

Download

Browse Figures

Figure 1
Functional diagram of the adder. "> Figure 2
Logic circuit of the adder on a MOSFET. "> Figure 3
Functional scheme of Ci transfer. "> Figure 4
Functional diagram of the Si calculator based on two addition schemes modulo two. "> Figure 5
Functional diagram of the Si calculator based on two addition schemes modulo two. "> Figure 6
Functional diagram of the conditional sum adder. "> Figure 7
Functional diagram of MUX1 multiplexer on the MOSFET. "> Figure 8
MUX2 multiplexer function diagram. "> Figure 9
Functional diagram of a multi–bit adder based on a single-bit conditional sum adder. ">

Versions Notes

Abstract

This paper provides an analysis of existing single-digit binary adders from the point of view of their implementation on fans built based on metal-oxide-semiconductor field-effect transistor—MOSFETs. The synthesis of a single-digit adder with a conditional sum is carried out. The considered adders are compared in terms of speed and hardware complexity (by the number of MOSFETs). Adders perform arithmetic operations on numbers. In combination with other logical operations, adders are the core of the circuits of arithmetic logic devices that implement several different operations; they are an integral part of different processors. The most important parameters of adders are their hardware complexity and performance; therefore, many options for single-bit and multi-bit connectors with serial, parallel and combined transmissions have been developed. In the final part, a scheme of a multi-bit adder with consecutive transfers on adders with a conditional sum is given. An example of performing addition operations is given.

Keywords:

single-bit adder; multi-bit adder with consecutive transfers; conditional sum adder; multiplexer

1. Introduction

Adders perform arithmetic addition and subtraction of numbers. Together with other logical operations, adders are the core of the circuits of arithmetic logic devices that implement a number of various operations (multiplication, division, etc.), which are an indispensable part of various processors.

Important parameters of adders are their hardware complexity and performance; therefore, many variants of single-bit and multi-bit adders with serial, parallel and combined transfers have been developed [1].

The listed adders are synthesized based on the truth table. The analytical expressions of the sum (S_i) and transfer functions C_i have the form:

S i = \bar{a_{i}} \bar{b_{i}} C_{i - 1} \lor \bar{a_{i}} b_{i} \bar{C_{i - 1}} \lor a_{i} \bar{b_{i}} \bar{C_{i - 1}} \lor a_{i} b_{i} C_{i - 1}; C_{i} = a_{i} b_{i} \lor a_{i} C_{i - 1} \lor b_{i} C_{i - 1},

(1)

where

\bar{a_{i}}

and

\bar{b_{i}}

are the i-th digits of the numbers A and B;

C_{i - 1}

—transfer from the junior category.

The formula can be reproduced on various sets of logic elements, such as AND-NOT, OR-NOT, “exclusive OR”, etc. At the same time, the hardware’s complexity and performance may be different.

2. Materials and Methods

The analysis of single-digit adders on elements is discussed below:

two-stage logic AND-OR-NOT [1];
two “exclusive OR” valves and OR-NOT and AND-NOT circuits [2];
three-way valve “exclusive OR” and circuits AND-NOT;
on valves “exclusive OR” and multiplexers, an adder with a conditional sum (conditional-sum addition_CSA) is implemented. Before determining the hardware complexity (the number of MOSFETs) and performance (the number of logic elements on which the signal is delayed), the circuits of the analyzed adders are depicted as logic gates on the MOSFET. Consider the analysis of an adder built on the basis of the two-stage logic AND-OR-NOT [1,3,4,5].

The circuit of such an adder is shown in Figure 1, and Figure 2 shows the circuit of this adder on the logic circuits of a MOSFET [6,7,8].

The analytical formula of the analyzed adder has the form:

C i_{} = (a_{i} b_{i} \lor a_{i} C_{i - 1} \lor b_{i} C_{i - 1}); S_{i} = \bar{C_{i - 1}} (a_{i} \lor b_{i} \lor C_{i - 1}) \lor a_{i} b_{i} C_{i - 1} .

(2)

Figure 1 shows the functional diagram of the adder constructed according to Formula (2).

Figure 2 shows its logic circuit on a MOSFET.

Figure 2 shows that the adder consists of six AND-NOT circuits with two inputs each. To implement them, 6 × 4 = 24 transistors will be required. It has nine circuits of NOT (2 × 9 = 18) transistors and a gate AND-NOT for 3 inputs (6 transistors), a gate OR-NOT for 3 inputs (6 transistors) and a gate OR-NOT for 4 inputs (8 transistors). In total, 62 MOSFETs will be required to implement the adder.

The time of formation of the transfer tci = 4 τ_le.

The time of formation of the sum Si = 7 τ_le.

The second single-digit adder [2,3,9], which is subject to analysis, refers to the following formula:

S_{i} = C_{i - 1} \oplus a_{i} \oplus {b;}_{i} C_{i} = \bar{a_{i} b_{i}} \bar{a_{i} c_{i - 1}} \bar{b_{i} c_{i - 1}} .

(3)

The functional scheme of the C_i transfer is shown in Figure 3, which consists of three two-input and one three-input AND-NOT circuit. To implement them, we will need (4 × 3) + 6 = 18 transistors. The time of transfer formation t_ci = 2 τ_le.

The S_i value in Formula (3) is calculated by adding modulo 2 (S_i¹ = a_i

\oplus

b_i), then S_i = S_i¹

\oplus

C_i−1 is calculated (the first option). Figure 4 shows a functional scheme for calculating S_i based on two addition schemes modulo two.

{S_{i}}^{1} = \bar{a_{i}} b_{i} \lor a_{i} \bar{b_{i}}; S_{i} = \bar{S_{i}^{1}} C_{i - 1} \lor S_{i}^{1} \bar{C_{i - 1}} .

(4)

Figure 4 shows that the implementation of S_i will require four inverters and six two-input AND-NOT circuits, which will require (4 × 2) + (6 × 4) = 30 transistors.

In total, to build an adder on two circuits modulo 2, we will need (18 + 32) = 50 transistors. The second adder can be built on the basis of an adder modulo two of three variables. In our case, a_i, b_i and C_i−1 come in as input variables. Then, the truth table for S_i has the form as shown in Table 1.

From this table we have:

{S_{i}}_{} = \bar{C_{i - 1}} \bar{a_{i}} b_{i} \lor \bar{C_{i - 1}} a_{i} \bar{b_{i}} \lor C_{i - 1} \bar{a_{i}} \bar{b_{i}} \lor C_{i - 1} a_{i} b_{i} .

(5)

To calculate S_i, the Formula (5) is transformed as follows:

{S_{i}}_{} = \overset{̿}{\bar{C_{i - 1}} \bar{a} b_{i} \lor \bar{C_{i - 1}} a_{i} {\bar{b_{i}}}_{i} \lor C_{i - 1} \bar{a_{i}} \bar{b_{i}} \lor C_{i - 1} a_{i} b_{i}} = \bar{\bar{(\bar{C_{i - 1}} \bar{a_{i}} b_{i})} (\bar{\bar{C_{i - 1}} a_{i} \bar{b_{i}})} (\bar{C_{i - 1} \bar{a_{i}} \bar{b_{i}})} (\bar{C_{i - 1} a_{i} b_{i})}} .

(6)

The functional scheme for the sum of S_i constructed according to the Formula (6) is shown in Figure 5.

According to Figure 5, it is not difficult to calculate that 38 MOSFETs will be required for the implementation of the S_i adder.

According to Figure 3, to calculate C_i, 18 transistors will be required for a total of 56 transistors. For the formation of S_i, a delay on 3 logical elements will be required, i.e., tsi = 3 τ_le.

Recently, the construction of so-called conditional sum adders (conditional-sum addition_ CSA) has been vigorously discussed [10,11,12,13,14].

The adder with a conditional sum is also built according to the truth table. Table 2 shows a modified table of the truth of the adder.

From the first part of Table 2, where C_i−1 = 0, we have

{S_{i}}^{0} = \bar{a_{i}} b_{i} \lor a_{i} \bar{b_{i}};

(7)

{C_{i}}^{0} = a_{i} b_{i} .

(8)

From the second part of Table 2, where C_i−1 = 0, we have

S_{i 1} = \bar{a_{i}} \bar{b_{i}} \lor a_{i} b_{i} .

(9)

C_{i 1} = \bar{a_{i}} b_{i} \lor a_{i} \bar{b_{i}} \lor a_{i} b_{i} = a_{i} \lor b_{i}

(10)

From this table it is also easy to see that

Si = \bar{S_{i}^{0}}

(11)

To construct the sum of S_i⁰ on the fans AND-NOT, OR-NOT and NOT, Formula (7) must be reduced to the form:

{S_{i}}^{0} = {(a}_{i} \lor b_{i}) (\bar{a_{i} b_{i}}) = \bar{\bar{{(a}_{i} \lor b_{i}) (\bar{a_{i} b_{i}})}} = \bar{(\bar{a_{i} \lor b_{i}}) + \bar{\bar{{(a}_{i} \lor b_{i})}}}

(12)

According to the Formulas (8), (10), (11) and (12) it is possible to put the functional sum of the adder on the conditional sum. At the same time, the functional circuit must be supplemented with multiplexers that are controlled by transferring from the lower digit to a selection of one of C_i⁰ and C_i¹ and one of S_i⁰ and S_i¹, forming a transfer to the next digit C_i and the value of the sum S_i.

Taking into account the above, the functional scheme of the adder has the form as the scheme shown in Figure 6.

The adder consists of two circuits, OR-NOT₁ and AND-NOT₂, three inverters, INV₁, INV₂ and INV₃, and a MUX₁ and MUX₂ multiplexer. At the inputs of the circuits OR-NOT₁ and AND-NOT₂, are the i-th digits a_i and b_i of the numbers A and B. At the output of the valve AND-NOT₂, the sum of S_i⁰ is formed, which is fed to the input “0” of the MUX₁ multiplexer and to the input of the inverter INV₂, and at its output, the sum of S_i is formed, which enters the input “1” MUX₁ multiplexer. From the output of the inverter INV₁, transfer C_i⁰ =

\bar{\bar{a_{i} b_{i}}} = a_{i} b_{i}

enters the input “0” of the MUX₂ multiplexer. From the output of the inverter INV₃ transfer:

{C_{i}}^{1} = \bar{\bar{a_{i} \lor b_{i}}} = a_{i} \lor b_{i}

(13)

It is fed to the input “1” of the MUX₂ multiplexer. The control inputs of the multiplexers are transferred from the lower-order C_i−1.

The adder works as follows. After the bits a_i and b_i are fed to the inputs of the gates OR-NOT₁ and AND-NOT₁, the value of S_i⁰ is formed at the output of the circuit OR-NOT₂, and the value of the sum S_i¹ is formed at the output of the inverter INV₂. At the same time, the transfer value C_i⁰ is formed at the output of the inverter INV₁ and the transfer value C_i¹ is formed at the output of the inverter INV₃.

After feeding the transfers C_i⁰ and C_i¹ and the sums S_i⁰ and S_i¹ at the input of the corresponding multiplexers by transferring C_i−1, which is fed to the control inputs of the multiplexers simultaneously, the value of the sum Si is formed at the output of the MUX₁ multiplexer and at the same time, the transfer C₁ is formed at the output of the MUX₂ multiplexer, which is fed to the inputs of the multiplexers of the next highest digit.

3. Result and Discussion

Figure 7 shows the functional diagram of the MUX₁ multiplexer on the MOSFET and the MUX₁ operation Table 3.

Figure 8 shows the functional diagram of the MUX₂ multiplexer and its operation table (Figure 8).

To build a CSA adder, an AND-NOT gate is required for two inputs (4 transistors), two OR-NOT gates for 2 inputs (2 × 4 = 8 transistors), 3 inverters INV₁/INV3 (3 × 2 = 6 transistors) and 2 multiplexers (2 × 6 = 12 transistors). Everything will be required for a total of 30 transistors (4 + 8 + 6 + 12 = 30 transistors). The S_i formation time is 4 τ_le and the delay time on multiplexers is 2 τ_le.

Table 4 shows an example of a truth table for MUX2, which is shown in Figure 8.

The order of operation of the bit adder with a conditional sum is given in Table 5.

From Figure 8, it is not difficult to calculate the number of transistors. To form the transfers of C_i⁰ and C_i¹ and the sums of S_i⁰ and S_i¹, 18 transistors are required. To build two multiplexers, 12 transistors are required.

Total Vtr = 18 + 12 = 30 transistors.

(14)

The maximum delay time for the formation of S_i⁰ and S_i¹ = 4τ_le, the delay time on parallel functioning multiplexers is −2τ_l7. A summary table of the main parameters for the considered adders is given in Table 6.

Table 6 shows that for the construction of a single-digit adder, the minimum number of transistors has an adder with a conditional sum. The same adder has a minimal delay in the formation of inter-bit transfers. An example of adding numbers to four-digit (N = 4) adders with a conditional sum is shown in Figure 9.

\begin{array}{l} Let A = a_{3} a_{2} a_{1} = 1 1 0 0_{2} \\ + \\ B = b_{3} b_{2} b_{1} 0 1 0 1_{2} \\ C_{0} = 1 \underline{1_{2}} \\ 1 0 0 1 0_{2} . \end{array}

(15)

Using Table 3, let us consider the operation of adding numbers A and B:

a₀ = 0 b₀ = 1 C₀ = 1.

According to the line 7 S₀⁰ = 1 S₀¹ = 0 and C₀⁰ = 0 C₀¹ = 1.

At the same time S₀ = 0 and C₁ = 1

1.: a₀ = 0 b₀ = 1 C₀ = 1

According to the line 7 S₀⁰ = 1 S₀¹ = 0 and C₀⁰ = 0 C₀¹ = 1

At the same time S₀ = 0 and C₁ = 1

2.: a₁ = 0 b₁ = 1 C₁ = 1

According to the line 5 S₁⁰ = 0 S₁¹ = 1 and C₁⁰ = 0 C₀¹ = 0

At the same time S₁ = 1 and C₂ = 0

3.: a₂ = 1 b₂ = 1 C₂ = 0

According to the line 4 S₂⁰ = 0 S₂¹ = 1 and C₂^p = 1 C₂¹ = 1

At the same time S₂ = 0 and C₂ = 1

4.: a₃ = 1 b₃ = 0 C₂ = 1

According to the line 7 S₃⁰ = 1 S₃¹ = 0 and C₃⁰ = 0 C₃¹ = 1

At the same time S₃ = 0 and C₄ = S₅ = 1

S_A+B = 10010₂ = 18₁₀

For N bit adders, T_sm = T_sm = nτ_MUX + 4τ_l.7.

By τ_MUX = 2τ_l7

T_sm = (2n + 4)τ_l7.

(16)

4. Conclusions

This paper analyzes adders built on the basis of the two-stage logic AND-OR-NOT and on the two- and three-input “exclusive OR” circuits, synthesizing a conditional sum adder. The main parameters (the number of MOSFETs and the speed of adders) are determined. It is shown that from the point of view of the number of transistors and the time of formation of inter-bit transfers, the conditional sum adder is advantageous. The efficiency of the adder is shown by an example. The final part shows a functional diagram of a four-digit adder with consecutive transfers.

Author Contributions

Conceptualization, S.T., A.M. (Assel Mukasheva), G.S., T.I., K.I. and T.I.; methodology, S.T., A.M. (Assel Mukasheva) and K.I.; software, K.I. and A.M. (Assel Mukasheva); validation, A.M. (Adil Mukhamedgali), G.S., T.I. and K.I.; formal analysis, S.T. and T.I.; investigation, S.T., A.M. (Adil Mukhamedgali), G.S. and T.I.; resources, S.T.; data curation, K.I. and A.M. (Adil Mukhamedgali); writing—original draft preparation, T.I. and G.S.; writing—review and editing, K.I., A.M. (Adil Mukhamedgali), G.S. and T.I.; visualization, K.I. and A.M. (Adil Mukhamedgali); supervision, T.I.; project administration, A.M. (Adil Mukhamedgali). All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

The data are not publicly available.

Conflicts of Interest

The authors declare no conflicts of interest.

References

Ugryumov, E.P. Digital Circuitry: Textbook. Handbook for Universities, 2nd ed.; BHV-Petersburg: St. Petersburg, Russia, 2005. [Google Scholar]
Lekhin, S.N. L52 Computer Circuitry; BHV-Petersburg: St. Petersburg, Russia, 2010. [Google Scholar]
Ercegovac, M.D.; Lang, T. Digital Arithmetic; Morgan Kaufmann Publishers: San Francisco, CA, USA, 2004. [Google Scholar]
Kartsev, M.A. Arithmetic of Digital Machines; Publishing House “SCIENCE”: Moscow, Russia, 1969; p. 676. [Google Scholar]
De Dinechin, F.; Ercegovac, M.D.; Muller, J.-M.; Revol, N. Digital Arithmetic; Wiley Encyclopedia of Computer Science and Engineering: Hoboken, NJ, USA, 2009. [Google Scholar] [CrossRef]
David, M.H.; Sarah, L.H. Digital Circuitry and Computer Architecture, 2nd ed.; Kaufman Morgan: New York, NY, USA, 2012. [Google Scholar]
Huang, Y.M.; Kuo, J.B. A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation. IEEE Trans. Circuit Syst. II Analog. Digit. Signal Process. 2000, 47, 1074–1079. [Google Scholar] [CrossRef]
Wang, Y.; Pai, C.; Song, X. The design of hybrid carry-lookahead/carry-select adders. IEEE Trans. Circuit Syst. II Analog. Digit. Signal Process. 2002, 49, 16–24. [Google Scholar] [CrossRef]
Patterson, D.; Hennessy, J.J. Computer Architecture and Design of Computer Systems, 4th ed.; Peter: St. Petersburg, Russia, 2012. [Google Scholar]
Sklansky, J. Conditional-Sum Addition Logic. IRE Trans. Electron. Comput. 1960, EC-9, 226–231. [Google Scholar] [CrossRef]
Lo, J.-J. Fast binary adder with conditional transfer generation. IEEE Trans. A Comput. 1997, 46, 248–253. [Google Scholar]
Niyazova, K.; Mukasheva, A.; Balbayev, G.; Iliev, T.; Mirambayeva, N.; Uzakbayev, M. Ant Colony Optimization Algorithm for Feature Selection in Suspicious Transaction Detection System. Eng. Proc. 2024, 60, 18. [Google Scholar] [CrossRef]
Cheng, K.-X.; Chen, S.-W. Improved the 32-bit conditional sum Adder for low-power high-speed applications. J. Inf. Sci. Eng. 2006, 22, 975–989. [Google Scholar]
Kossakov, M.; Mukasheva, A.; Balbayev, G.; Seidazimov, S.; Mukammejanova, D.; Sydybayeva, M. Quantitative Comparison of Machine Learning Clustering Methods for Tuberculosis Data Analysis. Eng. Proc. 2024, 60, 20. [Google Scholar] [CrossRef]

Figure 1. Functional diagram of the adder.

Figure 2. Logic circuit of the adder on a MOSFET.

Figure 3. Functional scheme of Ci transfer.

Figure 4. Functional diagram of the S_i calculator based on two addition schemes modulo two.

Figure 5. Functional diagram of the S_i calculator based on two addition schemes modulo two.

Figure 6. Functional diagram of the conditional sum adder.

Figure 7. Functional diagram of MUX₁ multiplexer on the MOSFET.

Figure 8. MUX₂ multiplexer function diagram.

Figure 9. Functional diagram of a multi–bit adder based on a single-bit conditional sum adder.

Table 1. The truth table for the sum of S_i.

C_i−1	a_i	b_i	S_i
0	0	0	0
0	0	1	1
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	0
1	1	1	1

Table 2. Modified adder truth table.

C_i−1	a_i	b_i	S_i⁰	S_i¹	C_i⁰	C_i¹
0	0	0	0	-	0	0
0	1	0	1	-	0	-
0	0	1	1	-	0	-
0	1	1	0	-	1	-
1	0	0	-	1	-	0
1	1	0	-	0	-	1
1	0	1	-	0	-	1
1	1	1	-	1	-	1

Table 3. Modified adder truth table.

C_i−1	S_i⁰	S_i⁰	S_i
0	0	1	0
0	1	0	1
1	0	1	1
1	1	0	1

Table 4. MUX₂ multiplexer truth table.

C_i−1	a_i	b_i	C_i⁰	C_i¹	C_i
0	0	0	0	0	0
0	0	1	0	1	0
0	1	0	0	1	0
0	1	1	1	1	1
1	0	0	0	0	0
1	0	1	0	1	1
1	1	0	0	1	1
1	1	1	1	1	1

Table 5. The order of operation of the adder with a conditional sum.

№	C_i−1	a_i	b_i	S_i⁰	S_i¹	C_i⁰	C_i¹	S_i	C_i
1	0	0	0	0	1	0	0	0	0
2	0	0	1	1	0	0	1	1	0
3	0	1	0	1	0	0	1	1	0
4	0	1	1	0	1	1	1	0	1
5	1	0	0	0	1	0	0	1	0
6	1	0	1	1	0	0	1	0	1
7	1	1	0	1	0	0	1	0	1
8	1	1	1	0	1	1	1	1	1

Table 6. The order.

Adders	Number of Transistors (N)	Time of Transfer Formation	Multiplexer Delay	Time of Sum Formation on n-bit Adder
Adder on two-stage logic (CM-1)	62	4 τ_le	-	7 nτ_le
Adder on two schemes “Excluding OR” (CM-3)	50	2 τ_le	-	6 nτ_le
Adder on a three-input circuit “Excluding OR” (CM-3)	56	2 τ_le	-	3 nτ_le
Conditional sum adder (CSA) (CM-4)	30	2 τ_le	2 τ_le	4 τ_le + nτ_MUX

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

© 2024 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

Share and Cite

MDPI and ACS Style

Tynymbayev, S.; Mukasheva, A.; Ibragimov, K.; Mukhamedgali, A.; Sergazin, G.; Iliev, T. Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers. Eng. Proc. 2024, 70, 6. https://doi.org/10.3390/engproc2024070006

AMA Style

Tynymbayev S, Mukasheva A, Ibragimov K, Mukhamedgali A, Sergazin G, Iliev T. Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers. Engineering Proceedings. 2024; 70(1):6. https://doi.org/10.3390/engproc2024070006

Chicago/Turabian Style

Tynymbayev, Sakhybay, Assel Mukasheva, Kuanyshbek Ibragimov, Adil Mukhamedgali, Gani Sergazin, and Teodor Iliev. 2024. "Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers" Engineering Proceedings 70, no. 1: 6. https://doi.org/10.3390/engproc2024070006

APA Style

Tynymbayev, S., Mukasheva, A., Ibragimov, K., Mukhamedgali, A., Sergazin, G., & Iliev, T. (2024). Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers. Engineering Proceedings, 70(1), 6. https://doi.org/10.3390/engproc2024070006

Article Menu

Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers^†

Abstract

1. Introduction

2. Materials and Methods

3. Result and Discussion

4. Conclusions

Author Contributions

Funding

Institutional Review Board Statement

Informed Consent Statement

Data Availability Statement

Conflicts of Interest

References

Share and Cite

Article Metrics

Article Access Statistics

Further Information

Guidelines

MDPI Initiatives

Follow MDPI

№	C_i−1	a_i	b_i	S_i⁰	S_i¹	C_i⁰	C_i¹	S_i	C_i
1	0	0	0	0	1	0	0	0	0
2	0	0	1	1	0	0	1	1	0
3	0	1	0	1	0	0	1	1	0
4	0	1	1	0	1	1	1	0	1
5	1	0	0	0	1	0	0	1	0
6	1	0	1	1	0	0	1	0	1
7	1	1	0	1	0	0	1	0	1
8	1	1	1	0	1	1	1	1	1

№	C_i−1	a_i	b_i	S_i⁰	S_i¹	C_i⁰	C_i¹	S_i	C_i
1	0	0	0	0	1	0	0	0	0
2	0	0	1	1	0	0	1	1	0
3	0	1	0	1	0	0	1	1	0
4	0	1	1	0	1	1	1	0	1
5	1	0	0	0	1	0	0	1	0
6	1	0	1	1	0	0	1	0	1
7	1	1	0	1	0	0	1	0	1
8	1	1	1	0	1	1	1	1	1

Article Menu

Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers †

Abstract

1. Introduction

2. Materials and Methods

3. Result and Discussion

4. Conclusions

Author Contributions

Funding

Institutional Review Board Statement

Informed Consent Statement

Data Availability Statement

Conflicts of Interest

References

Share and Cite

Article Metrics

Article Access Statistics

Further Information

Guidelines

MDPI Initiatives

Follow MDPI

Analysis and Synthesis of Single-Bit Adders for Multi-Bit Adders with Sequential Transfers^†

№	C_i−1	a_i	b_i	S_i⁰	S_i¹	C_i⁰	C_i¹	S_i	C_i
1	0	0	0	0	1	0	0	0	0
2	0	0	1	1	0	0	1	1	0
3	0	1	0	1	0	0	1	1	0
4	0	1	1	0	1	1	1	0	1
5	1	0	0	0	1	0	0	1	0
6	1	0	1	1	0	0	1	0	1
7	1	1	0	1	0	0	1	0	1
8	1	1	1	0	1	1	1	1	1