Article

A reconfigurable unit for a clustered programmable-reconfigurable processor

Authors:

Richard B. Kujoth,

Derek B. Gottlieb,

Jeffrey J. Cook,

Nicholas P. CarterAuthors Info & Claims

FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Pages 200 - 209

https://doi.org/10.1145/968280.968309

Published: 22 February 2004 Publication History

Abstract

In a clustered programmable-reconfigurable processor, multiple programmable processors and blocks of reconfigurable logic communicate through a register-based communication mechanism, which reduces the impact of wire delay on clock cycle time. In this paper, we present a circuit-level design for the reconfigurable clusters used on the Amalgam programmable-reconfigurable processor. We outline our interleaved reconfigurable array design, which provides high bandwidth to and from the register file without requiring large amounts of register control logic. We characterize the latency of operations in our array, and present results that show the impact that this latency has on overall system performance in a range of fabrication processes. Finally, we present a pipelining scheme that enables the array to operate at clock rates closer to those of programmable processors and allows for better scaling in future technologies.

References

[1]

NCSU Cadence Design Kit. http://www.cadence.ncsu.edu/.

[2]

S. Borkar. Design Challenges of Technology Scaling. Proceedings of the International Symposium on Microarchitecture, 19(4):23--29, July 1999.

Digital Library

[3]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, and I. Rahardja. The Design of a SRAM-Based Field-Programmable Gate Array--Part II: Circuit Design and Layout. IEEE Transactions on VLSI Systems, 7(3):321--330, Sept. 1999.

Digital Library

[4]

D. Cronquist, P. Franklin, C. Fisher, M. Figueroa, and C. Ebeling. Architecture Design of Reconfigurable Pipelined Datapaths. In Proceedings of the Twentieth Anniversary Conference on Advanced Research in VLSI, pages 23--40, 1999.

Digital Library

[5]

S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer. PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In Proceedings of the International Symposium on Computer Architecture, pages 28--38, 1999.

Digital Library

[6]

D. B. Gottlieb, J. J. Cook, J. D. Walstrom, S. Ferrera, C.-W. Wang, and N. P. Carter. Clustered Programmable-Reconfigurable Processors. In Proceedings of the IEEE International Conference on Field-Programmable Technology, pages 134--141. IEEE, Dec. 2002.

[7]

S. Gupta, S. W. Keckler, and D. Burger. Technology Independent Area and Delay Estimates for Microprocessor Building Blocks. Technical Report 2000-05, Department of Computer Sciences, The University of Texas at Austin, 2000.

Digital Library

[8]

S. Hauck, M. M. Hosler, and T. W. Fry. High-Performance Carry Chains for FPGA's. IEEE Transactions on VLSI Systems, 8(2):138--147, Apr. 2000.

Digital Library

[9]

J. R. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In KL. Pocek and JArnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, pages 12--21, Los Alamitos, CA, 1997. IEEE Computer Society Press.

Digital Library

[10]

R. Ho, K. W. Mai, and M. A. Horowitz. The Future of Wires. Proceedings of the IEEE, 89(4):490--504, Apr. 2001.

[11]

MHrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, S. W. Keckler, and P. Shivakumar. The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Delays. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 14--24. IEEE, May 2002.

Digital Library

[12]

The International Technology Roadmap for Semiconductors 2001. Semiconductor Industry Association, 2001.

[13]

The International Technology Roadmap for Semiconductors 2002 Update. Semiconductor Industry Association, 2002.

[14]

J. Rose, R. J. Francis, D. Lewis, and P. Chow. Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency. IEEE Journal of Solid-State Circuits, 25(5):1217--1225, Oct. 1990.

[15]

I. Sutherland, B. Sproull, and D. Harris. Logical Effort: Designing Fast Cmos Circuits. Morgan Kaufmann Publishers, San Francisco, CA, 1999.

Digital Library

[16]

J. D. Walstrom. The Design of the Amalgam Reconfigurable Cluster. Master's thesis, University of Illinois at Urbana-Champaign, 2002.

[17]

S.-C. Wong, G.-Y. Lee, and D.-J. Ma. Modeling of Interconnect Capacitance, Delay, and Crosstalk in VLSI. IEEE Transactions on Semiconductor Manufacturing, 13(1):108--111, February 2000.

[18]

Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee. CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit. In Proceedings of the International Symposium on Computer Architecture, pages 225--235, 2000.

Digital Library

Cited By

Machanick PBarnard LBotha R(2007)Design principles for a virtual multiprocessorProceedings of the 2007 annual research conference of the South African institute of computer scientists and information technologists on IT research in developing countries10.1145/1292491.1292500(76-82)Online publication date: 2-Oct-2007
https://dl.acm.org/doi/10.1145/1292491.1292500
Kujoth RWang CCook JGottlieb DCarter N(2007)A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processorMicroprocessors & Microsystems10.1016/j.micpro.2006.03.00131:2(146-159)Online publication date: 1-Mar-2007
https://dl.acm.org/doi/10.1016/j.micpro.2006.03.001
Chi-Wei Wang Carter NKujoth RCook JGottlieb D(2005)Exploiting pipelining to tolerate wire delays in a programmable-reconfigurable processorInternational Conference on Field Programmable Logic and Applications, 2005.10.1109/FPL.2005.1515699(57-64)Online publication date: 2005
https://doi.org/10.1109/FPL.2005.1515699

Index Terms

A reconfigurable unit for a clustered programmable-reconfigurable processor
1. Computer systems organization
  1. Architectures
2. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

Recommendations

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of ...
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor

Wire delay is rapidly becoming a major bottleneck in reconfigurable systems, creating a significant gap between the clock rates of reconfigurable logic and custom circuits. In this paper, we describe the design of the reconfigurable clusters on the ...
Dynamically reconfigurable register file for a softcore VLIW processor
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

This paper presents dynamic reconfiguration of a register file of a Very Long Instruction Word (VLIW) processor implemented on an FPGA. We developed an open-source reconfigurable and parameterizable VLIW processor core based on the VLIW Example (VEX) ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

February 2004

266 pages

ISBN:1581138296

DOI:10.1145/968280

General Chair:
Russ Tessier
University of Massachusetts -- Amherst
,
Program Chair:
Herman Schmit
Everychip, Inc.

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2004

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

FPGA04

Sponsor:

FPGA04: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2004

February 22 - 24, 2004

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
761
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 19 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Machanick PBarnard LBotha R(2007)Design principles for a virtual multiprocessorProceedings of the 2007 annual research conference of the South African institute of computer scientists and information technologists on IT research in developing countries10.1145/1292491.1292500(76-82)Online publication date: 2-Oct-2007
https://dl.acm.org/doi/10.1145/1292491.1292500
Kujoth RWang CCook JGottlieb DCarter N(2007)A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processorMicroprocessors & Microsystems10.1016/j.micpro.2006.03.00131:2(146-159)Online publication date: 1-Mar-2007
https://dl.acm.org/doi/10.1016/j.micpro.2006.03.001
Chi-Wei Wang Carter NKujoth RCook JGottlieb D(2005)Exploiting pipelining to tolerate wire delays in a programmable-reconfigurable processorInternational Conference on Field Programmable Logic and Applications, 2005.10.1109/FPL.2005.1515699(57-64)Online publication date: 2005
https://doi.org/10.1109/FPL.2005.1515699

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents