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Design principles for a virtual multiprocessor

Published: 02 October 2007 Publication History

Abstract

The case for chip multiprocessor (CMP) or multicore designs is strong, and increasingly accepted as evidenced by the growing number of commercial multicore designs. However, there is also some evidence that the quest for instruction-level parallelism, like the Monty Python parrot, is not dead but resting. The cases for CMP and ILP are complementary. A multitasking or multithreaded workload will do better on a CMP design; a floating-point application without many decision points will do better on a machine with ILP as its main parallelism. This paper explores a model for achieving both in the same design, by reconfiguring functional units on the fly. The result is a virtual multiprocessor (or vMP) which at the software level looks like either a uniprocessor with n clusters of functional units, or an n-core CMP, depending on how the data path is configured.

References

[1]
C. Albrecht, J. Foag, R. Koch, and E. Maehle. DynaCORE---a dynamically reconfigurable coprocessor architecture for network processors. In Proc. 14th Euromicro Int. Conf. on Parallel, Distributed, and Network-Based Processing (PDP'06), pages 101--108, Montbéliard, France, February 2006.
[2]
AMD. Multi-core processors---the next evolution in computing. Technical report, AMD, 2005.
[3]
A. J. Elbirt and C. Paar. An instruction-level distributed processor for symmetric-key cryptography. IEEE Trans. on Parallel and Distributed Systems, 16(5):468--480, May 2005.
[4]
K. I. Farkas, P. Chow, N. P. Jouppi, and Z. Vranesic. The multicluster architecture: reducing cycle time through partitioning. In Proc. 30th Ann. ACM/IEEE Int. Symp. on Microarchitecture, pages 149--159, Research Triangle Park, NC, 1997.
[5]
E. Gibert, J. Sánchez, and A. González. An interleaved cache clustered VLIW processor. In ICS '02: Proc. 16th Int. Conf. on Supercomputing, pages 210--219, 2002.
[6]
S. Gochman, A. Mendelson, A. Naveh, and E. Rotem. Introduction to intel core duo processor architecture. Intel Technology J., 10(2), May 2006. ftp://download.intel.com/technology/itj/2006/volume10issue02/vol10_art01.pdf.
[7]
R. González, A. Cristal, M. Pericas, M. Valero, and A. Veidenbaum. An asymmetric clustered processor based on value content. In ICS '05: Proc. 19th Ann. Int. Conf. on Supercomputing, pages 61--70, 2005.
[8]
D. Graham-Rowe. Logic from chaos: New chips use chaos to produce potentially faster, more robust computing. Technology Review, June 2006. http://www.technologyreview.com/read_article. aspx?id=16989&ch=biztech.
[9]
L. Hammond, B. A. Hubbert, M. Siu, M. K. Prabhu, M. Chen, and K. Olukotun. The Stanford Hydra CMP. IEEE Micro, 20(2):71--84, March/April 2000.
[10]
IBM. Ibm powerpc 970mp risc microprocessor userÕs manual. Technical report, IBM, 2006.
[11]
A. Jerraya and W. Wolf. Hardware/software interface code-sign for embedded systems. Computer, 38(2):63--69, February 2005.
[12]
J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy. Introduction to the Cell multiprocessor. IBM J. of Research and Development, 49(4/5):589--604, July-September 2005.
[13]
R. E. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24--36, March-April 1999.
[14]
T. Kgil, S. D'Souza, A. Saidi, N. Binkert, R. Dreslinski, S. Reinhardt, K. Flautner, and T. Mudge. Picoserver: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor. In Proc. 12th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 117--128, San Jose, CA, October 2006.
[15]
R. B. Kujoth, C.-W. Wang, D. B. Gottlieb, J. J. Cook, and N. P. Carter. A reconfigurable unit for a clustered programmable-reconfigurable processor. In FPGA '04: Proc. 2004 ACM/SIGDA 12th Int. Symp. on Field Programmable Gate Arrays, pages 200--209, 2004.
[16]
R. Kumar, K. Farkas, N. Jouppi, P. Ranganathan, and D. Tullsen. Processor power reduction via single-ISA heterogeneous multi-core architectures. Computer Architecture Letters, 2(1):2--5, July 2003.
[17]
D. Marculescu. Application adaptive energy efficient clustered architectures. In ISLPED '04: Proc. 2004 Int. Symp. on Low Power Electronics and Design, pages 344--349, 2004.
[18]
K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The case for a single-chip multiprocessor. In Proc. 7th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-7), pages 2--11, Cambridge, MA, October 1996.
[19]
E. Özer, S. Banerjia, and T. M. Conte. Unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures. In MICRO 31: Proc. 31st Ann. ACM/IEEE Int. Symp. on Microarchitecture, pages 308--315, 1998.
[20]
P. Salverda and C. Zilles. A criticality analysis of clustering in superscalar processors. In MICRO 38: Proc. 38th Ann. IEEE/ACM Int. Symp. on Microarchitecture, pages 55--66, Barcelona, Spain, 2005.
[21]
B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Joyner. POWER5 system microarchitecture. IBM J. of Research and Development, 49(4/5):505--521, July/September 2005. http://www.research.ibm.com/journal/rd/494/sinharoy.pdf.
[22]
J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy. POWER4 system microarchitecture. IBM J. of Research and Development, 46(1):5--25, January 2002. http://researchweb.watson.ibm.com/journal/rd/461/tendler.pdf.
[23]
B. F. Veale, J. K. Antonio, and M. P. Tull. Configuration steering for a reconfigurable superscalar processor. In Proc. 19th IEEE Int. Parallel and Distributed Processing Symp. (IPDPSÕ05) -- Workshop 3, page 152b, Denver, Colorado, 2005.
[24]
Z. Wang, X. S. Hu, and E. H.-M. Sha. Register aware scheduling for distributed cache clustered architecture. In ASPDAC: Proc. 2003 Conf. on Asia South Pacific Design Automation, pages 71--76, 2003.
[25]
J. Zalamea, J. Llosa, E. Ayguadé, and M. Valero. Modulo scheduling with integrated register spilling for clustered VLIW architectures. In MICRO 34: Proc. 34th Ann. ACM/IEEE Int. Symp. on Microarchitecture, pages 160--169, 2001.

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Published In

cover image ACM Other conferences
SAICSIT '07: Proceedings of the 2007 annual research conference of the South African institute of computer scientists and information technologists on IT research in developing countries
October 2007
211 pages
ISBN:9781595937759
DOI:10.1145/1292491
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 02 October 2007

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  1. chip multiprocessor
  2. instruction-level parallelism

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SAICSIT '07
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